Versatile reconfigurable matrix based built-in self-test processor for minimizing fault grading

• US 5,485,467 A
• Filed: 09/24/1993
• Issued: 01/16/1996
• Est. Priority Date: 09/24/1993
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Golnabi, Habibollah
• Primary Examiner(s): Voeltz, Emanuel T.
• Assistant Examiner(s): PIPALA, EDWARD J
• Application Number:
  US08/127,270
• Time in Patent Office: 844 Days
• Field of Search: 371/22.3, 371/15.1, 371/10.3, 371/22.4, 371/22.5, 371/22.1, 371/22.6, 395/150, 395/162, 395/164, 395/166
• US Class Current: 714/733
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's

Abstract

A built-in self-test circuitry includes a design under test and a self-test processor. Included within the design under test is a plurality of scan row registers. The self-test processor includes a command processing section and a signal generating section. The command processing section receives information which indicates the configuration of the scan row registers. The signal generating section generates control signals which control the built-in self-testing of the circuit. The control signals are based on the information received by the command processing section. In the preferred embodiment, the command processing section includes a shift section, a load section, and a signature section. The shift section receives information which indicates a number of bits in each scan row register. The load section receives information which indicates a number of loads into the scan row registers. The signature section receives information which indicates a bit length of signature registers used to generate a checksum. The signature section additionally receives information which indicates a number of scan row registers.

Claims

1. A method for controlling built-in self-testing of a circuit in which during self-testing scan row registers within the circuit provide input to combination logic and output from the combination logic is utilized to generate a checksum, the method comprising the steps of:

(a) receiving, by a self-test processor within the circuit, configuration information which indicates the configuration of the scan row registers, the configuration information including information which indicates a number of bits in each scan row register; and

,

(b) generating, by the self-test processor, control signals which control the built-in self-testing of the circuit, the control signals including signals which control data transfer to the scan row register, the control signals being based on the configuration information received in step (a).

2. A method as in claim 1 wherein step (a) includes the following substep:

(a.1) receiving, by the self-test processor within the circuit, information which indicates a number of scan row registers.

3. A method as in claim 2 wherein step (a) additionally includes the substep of:

(a.2) receiving, by the self-test processor within the circuit, information which indicates a bit length of signature registers used to generate a checksum.

4. A method as in claim 3 wherein step (a) additionally includes the substep of:

(a.3) receiving, by the self-test processor within the circuit, information which indicates a number of loads into the scan row registers.

5. Built-in self-test circuitry within an integrated circuit, the built-in self-test circuitry comprising:

a design under test including a plurality of scan row registers; and

,

a self-test processor, coupled to the design under test, the self-test processor including;

command processing means for receiving configuration information which indicates the configuration of the scan row registers, the configuration information including information which indicates a number of bits in each scan row register, and

signal generating means, coupled to the command processing means, for generating control signals which control the built-in self-testing of the circuit, the control signals being based on the configuration information received by the command processing means.

6. Built-in self-test circuitry as in claim 5 wherein the command processing means includes:

shift means for receiving the information which indicates the number of bits in each scan row register.

7. Built-in self-test circuitry as in claim 6 wherein the command processing means additionally includes:

load means for receiving information which indicates a number of loads into the scan row registers.

8. Built-in self-test circuitry as in claim 7 wherein the command processing means additionally includes:

signature means for receiving information which indicates a bit length of signature registers used to generate a checksum and for receiving information which indicates a number of scan row registers.