Method and circuitry for clock synchronization

• US 5,485,490 A
• Filed: 11/29/1994
• Issued: 01/16/1996
• Est. Priority Date: 05/28/1992
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Leung, Wingyu, Horowitz, Mark A.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Bocure, Tesfaldet
• Application Number:
  US08/346,363
• Time in Patent Office: 413 Days
• Field of Search: 375/118, 375/119, 307/1, 307/2, 307/3, 307/144, 329/109, 329/63, 329/137, 329/155, 329/133
• US Class Current: 375/371
• CPC Class Codes: H03K 3/0231 Astable circuits H03K3/0315 takes precedence
• CPC Class Codes: H03K 3/0322 with differential cells
• CPC Class Codes: H03K 3/354 Astable circuits
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0996 Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

Circuitry for performing fine phase adjustment within a phase locked loop is described. The phase selector selects an even phase signal and an odd phase signal from the twelve phase signals output by the VCO. The even and odd phase signals are selected by an even select signal and an odd select signal, respectively. The phase interpolator interpolates between the even phase signal and the odd phase signal to generate an output signal. The affect of the even phase signal and the odd phase signal on the output signal is determined by an even weighting signal and an odd weighting signal, respectively. The weighting signals prevent glitches from appearing on the output signal when either the even phase signal or the odd phase signal is switching. A method of performing fine phase adjustment in a phase locked loop is also described.

Claims

1. A method of performing phase adjustment in a phase locked loop to generate a first output phase signal from a multiplicity of input phase signals, comprising the steps of:

a) selecting a first phase signal and a second phase signal from the multiplicity of input phase signals in response to a select signal;

b) generating a weighting signal in response to a control signal, wherein the control signal causes the weighting signal to control interpolation between the first and second phase signals when the select signal is changing states, wherein the select signal is generated in response to the control signal; and

c) interpolating between the first phase signal and the second phase signal to generate the first output phase signal in response to the weighting signal.

2. The method of claim 1, further comprising the step of:

a) generating the multiplicity of input phase signals from a clock signal having a frequency F, each of the multiplicity of input phase signals having the frequency F.

3. The method of claim 2 further comprising the step of:

a) generating the select signal from the control signal.

4. The method of claim 1 further comprising the steps of:

a) selecting a third phase signal and a fourth phase signal from the multiplicity of input phase signals in response to the select signal; and

b) interpolating between the third phase signal and the fourth phase signal to generate a second output phase signal in response to the weighting signal, the second output phase signal leading the first output phase signal by substantially 90°

.

5. A method of performing phase adjustment in a phase locked loop to generate a first output phase signal from a multiplicity of even phase signals and a multiplicity of odd phase signals, comprising the steps of:

a) selecting a first even phase signal from the multiplicity of even phase signals in response to an even select signal;

b) selecting a first odd phase signal from the multiplicity of odd phase signals in response to an odd select signal, wherein each of the even and odd select signals is generated in response to a control signal;

c) generating an even weighting signal and an odd weighting signal in response to the control signal, wherein the control signal causes the even and odd weighting signals to control interpolation between the first even and first odd phase signals when one of the first even and odd select signals is changing states; and

d) interpolating between the first even phase signal and the first odd phase signal to generate the first output phase signal in response to the even weighting signal and the odd weighting signal, the even weighting signal preventing the first even phase signal from contributing to the first output phase signal when the even select signal is changing states, and the odd weighting signal preventing the first odd phase signal from contributing to the first output phase signal when the odd select signal is changing states.

6. The method of claim 5 further comprising the steps of:

a) selecting a second even phase signal from the multiplicity of even phase signals in response to the even select signal;

b) selecting a second odd phase signal from the multiplicity of odd phase signals in response to the odd select signal; and

c) interpolating between the second even phase signal and the second odd phase signal to generate a second output phase signal in response to the even weighting signal and the odd weighting signal, the second output phase signal leading the first output phase signal by substantially 90°

, the even weighting signal preventing the second even phase signal from contributing to the second output phase signal when the even select signal is changing states, and the odd weighting signal preventing the second odd phase signal from contributing to the second output phase signal when the odd select signal is changing states.

7. The method of claim 5 further comprising the step of:

a) generating the multiplicity of even phase signals and the multiplicity of odd phase signals in response to an input signal having a frequency F, the multiplicity of even phase signals and multiplicity of the odd phase signals having the frequency F.

8. The method of claim 5 further comprising the steps of:

a) generating a shift left signal and a shift right signal in response to the control signal;

b) generating the even select signal in response to the shift left signal and the shift right signal; and

c) generating the odd select signal in response to the shift left signal and the shift right signal.

9. Phase tuning circuitry for generating an output phase signal from a multiplicity of input phase signals, comprising:

a) a select circuit for generating a select signal in response to a control signal;

b) a weighting circuit for generating a weighting signal in response to the control signal;

c) a phase selector for selecting a first phase signal and a second phase signal from the multiplicity of input phase signals in response to the select signal; and

d) a phase interpolator for interpolating between the first phase signal and the second phase signal to generate the output phase signal in response to the weighting signal, wherein the weighting signal is used to control interpolation between the first and second phase signals when the select signal is changing states, wherein the select signal and the weighting signal are generated in response to the control signal.

10. The phase tuning circuitry of claim 9 wherein the phase selector further comprises:

a) a barrel shifter generating the select signal in response to the control signal.

11. The phase tuning circuitry of claim 10 wherein the phase selector further comprises:

a) a first multiplexing circuit for selecting the first phase signal from the multiplicity of input phase signals in response to the select signal; and

b) a second multiplexing circuit for selecting the second phase signal from the multiplicity of input phase signals in response to the select signal.

12. The phase tuning circuitry of claim 9 wherein the phase interpolator comprises:

a) a first differential amplifier coupled to the first phase signal and the weighting signal, the first differential amplifier having a first output coupled to the output phase signal; and

b) a second differential amplifier coupled to the second phase signal and the weighting signal, the second differential amplifier having a second output coupled to the first output.

13. Phase tuning circuitry for generating an output phase signal from a multiplicity of even phase signals and a multiplicity of odd phase signals, the phase tuning circuitry comprising:

a) a select signal generator for generating an even select signal and an odd select signal in response to a control signal;

b) a weighting signal generator for generating an even weighting signal and an odd weighting signal in response to the control signal;

c) a phase selector for selecting an even phase signal from the multiplicity of even phase signals in response to an even select signal and for selecting an odd phase signal from the multiplicity of odd phase signals in response to an odd select signal; and

d) a phase interpolator for interpolating between the even phase signal and the odd phase signal to generate the output phase signal in response to the even weighting signal and the odd weighting signal, wherein the control signal causes the even and odd weighting signals to control interpolation between the even and odd phase signals when one of the even and odd select signals is changing states, the even weighting signal preventing the even phase signal from contributing to the output phase signal when the even select signal is changing states, and the odd weighting signal preventing the odd phase signal from contributing to the output phase signal when the odd select signal is changing states.

14. The phase tuning circuitry of claim 13 further comprising:

a) control circuitry responsive to the control signal for generating the even select signal, the odd select signal, the even weighting signal and the odd weighting signal.

15. The phase tuning circuitry of claim 14 wherein the phase selector comprises:

a) a first barrel shifter generating the even select signal in response to the control signal; and

b) a second barrel shifter generating the odd select signal in response to the control signal.

16. The phase tuning circuitry of claim 15 wherein the phase selector further comprises:

a) a first multiplexing means for selecting the even phase signal from the multiplicity of even phase signals in response to the even select signal; and

b) a second multiplexing means for selecting the odd phase signal from the multiplicity of odd phase signals in response to the odd select signal.

17. The phase tuning circuitry of claim 16 wherein the phase interpolator comprises:

a) a first differential amplifier coupled to the even phase signal and the even weighting signal, the first differential amplifier having a first output; and

b) a second differential amplifier coupled to the odd phase signal and the odd weighting signal, the second differential amplifier having a second output coupled to the first output.

18. The phase tuning circuitry of claim 13 further comprising:

a) a phase locked loop for generating the multiplicity of even phase signals and the multiplicity of odd phase signals.

19. The phase tuning circuitry of claim 13, wherein the phase tuning circuitry is coupled to a data input circuit, the data input circuit receiving a data input signal from which the data input circuit generates the multiplicity of even phase signals and the multiplicity of odd phase signals, the data input signal having a delay, wherein the phase tuning circuitry further comprises:

a) circuitry for compensating for the delay associated with the data input circuit.

20. The phase tuning circuitry of claim 13, wherein the output phase signal is coupled to an output buffer having a delay, and wherein the phase tuning circuitry further comprises:

a) circuitry for compensating for the delay associated with the output buffer.

21. Phase tuning circuitry for generating an output phase signal from a multiplicity of even phase signals and a multiplicity of odd phase signals, the phase tuning circuitry having fast power up and power down response characteristics, the phase tuning circuitry comprising:

a) a select signal generator for generating an even select signal and an odd select signal in response to a control signal;

b) a weighting signal generator for generating an even weighting signal and an odd weighting signal in response to the control signal;

c) a phase selector for selecting an even phase signal from the multiplicity of even phase signals in response to the even select signal and for selecting an odd phase signal from the multiplicity of odd phase signals in response to the odd select signal; and

d) a phase interpolator for interpolating between the even phase signal and the odd phase signal to generate the output phase signal in response to the even weighting signal and the odd weighting signal wherein the control signal causes the even and odd weighting signals to control interpolation between the even and odd phase signals when one of the even and odd select signals is changing states, the even weighting signal preventing the even phase signal from contributing to the output phase signal when the even select signal is changing states, and the odd weighting signal preventing the odd phase signal from contributing to the output phase signal when the odd select signal is changing states.

22. Phase tuning circuitry for generating an output phase signal, comprising:

a) an accumulator for generating an underflow/overflow signal and a count signal in response to a control signal;

b) a digital to analog converter for generating an even weighting signal and an odd weighting signal in response to the count signal;

c) control circuitry for generating a barrel shift control signal in response to the underflow/overflow signal;

d) a first barrel shifter generating a multiplicity of even select signals in response to the barrel shift control signal; and

e) a second barrel shifter generating a multiplicity of odd select signals in response to the barrel shift control signal;

f) a phase selector comprising;

i) a first multiplexing means for selecting an even phase signal from a multiplicity of even phase signals in response to the multiplicity of even select signals;

ii) a second multiplexing means for selecting an odd phase signal from a multiplicity of odd phase signals in response to the multiplicity of odd select signals; and

g) a phase interpolator for interpolating between the even phase signal and the odd phase signal to generate the output phase signal, the phase interpolator comprising;

i) a first differential amplifier coupled to the even phase signal and the even weighting signal, the even weighting signal preventing the even phase signal from contributing to the output phase signal when the even select signal is changing states, the first differential amplifier having a first output; and

ii) a second differential amplifier coupled to the odd phase signal and the odd weighting signal, the odd weighting signal preventing the odd phase signal from contributing to the output phase signal when the odd select signal is changing states, the second differential amplifier having a second output coupled to the first output.

23. The circuitry of claim 22 further comprising:

a) a voltage controlled oscillator receiving an input signal and generating the multiplicity of even phase signals and the multiplicity of odd phase signals.

24. The circuitry of claim 22 further comprising:

a) a phase locked loop for receiving the input signal and generating the multiplicity of even phase signals and the multiplicity of odd phase signals.