Flash memory mass storage architecture incorporating wear leveling technique without using cam cells

• US 5,485,595 A
• Filed: 10/04/1993
• Issued: 01/16/1996
• Est. Priority Date: 03/26/1993
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Mozaffari, Mahmood, Estakhri, Petro, Nemazie, Siamack, Assar, Mahmud
• Primary Examiner(s): Gossage, Glenn
• Assistant Examiner(s): BRAGDON, REGINALD GLENWOOD
• Application Number:
  US08/131,495
• Time in Patent Office: 834 Days
• Field of Search: 395/425, 365/185, 365/218, 365/900, 365/189.07
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/105 Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A semiconductor mass storage device can be substituted for a rotating hard disk. The device avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. Secondly, a circuit and method are provided for evenly using all blocks in the mass storage. These advantages are achieved through the use of several flags, a map to correlate a logical address of a block to a physical address of that block and a count register for each block. In particular, flags are provided for defective blocks, used blocks, old versions of a block, a count to determine the number of times a block has been erased and written and an erase inhibit flag. Reading is performed by providing the logical block address to the memory storage. The system sequentially compares the stored logical block addresses until it finds a match. That data file is then coupled to the system.

Claims

1. A non-volatile semiconductor mass storage device comprising:

a. a plurality of non-volatile data blocks, wherein each one of the plurality of non-volatile data blocks is selectively programmable and erasable and further wherein only those of the plurality of non-volatile data blocks that contain no data can be programmed;

b. a plurality of non-volatile information blocks for storing status information, each of said plurality of non-volatile information blocks directly corresponding to an appropriate one of the plurality of non-volatile data blocks, each of said plurality of non-volatile information blocks including a first flag which is indicative that a corresponding appropriate one of the plurality of non-volatile data blocks has been programmed, and further wherein an address of each one of a plurality of logical blocks corresponds to a physical address of the appropriate one of the plurality of non-volatile data blocks;

c. a comparator coupled to the plurality of non-volatile information blocks for determining whether any unprogrammed one of the plurality of non-volatile data blocks remain;

d. a controller coupled to the comparator for setting a first flag;

e. the controller for periodically erasing all of the plurality of non-volatile data blocks having first flags which are set;

f. a storage programmer for storing a logical block address associated with each one of the plurality of non-volatile data blocks within an appropriate one of the plurality of non-volatile information blocks forming a stored logical block address, whereby an erase cycle is not needed each time an updated block replaces a superseded data block; and

g. means for reading the non-volatile semiconductor mass storage device, comprising means for coupling a desired logical block address to the non-volatile semiconductor mass storage device and means for sequentially comparing the desired logical block address to each of the stored logical block addresses.

2. The non-volatile semiconductor mass storage device according to claim 1 wherein the first flag and the logical block address are stored in non-volatile memory.

3. The non-volatile semiconductor mass storage device according to claim 2 wherein the first flag and the logical block address are also stored in volatile memory.

4. The non-volatile semiconductor mass storage device according to claim 3 wherein the status information stored in the plurality of non-volatile information blocks is copied to the volatile memory during a power-up and a system reset.

5. The non-volatile semiconductor mass storage device according to claim 1 wherein the controller for periodically erasing simultaneously erases all blocks having first flags which are set.

6. The non-volatile semiconductor mass storage device according to claim 5 wherein the controller for periodically erasing comprises a plurality of non-volatile single bit storage cells, one non-volatile single bit storage cell for each of the plurality of non-volatile data blocks and coupled to each of the plurality of non-volatile data blocks, each one of the plurality non-volatile single bit storage cells for storing a second flag and a plurality of volatile latches, one for each of the plurality of non-volatile single bit storage cells, each volatile latch coupled to receive a logic state of the plurality of non-volatile single bit storage cells during an erase cycle.

7. The non-volatile semiconductor mass storage device according to claim 3 wherein the volatile memory comprises RAM cells.

8. The non-volatile semiconductor mass storage device according to claim 7 wherein the RAM cells are SRAM cells.

9. The non-volatile semiconductor mass storage device according to claim 8 further comprising means for ensuring which comprises a counter for each block for counting each erase cycle to which that block has been subjected.

10. The non-volatile semiconductor mass storage device according to claim 9 further comprising means for setting a predetermined maximum count value for each of the plurality of non-volatile information blocks and means for storing a count value in each information block for preventing one of the plurality of non-volatile data blocks from being programmed more than a maximum number of times relative to all other of the plurality of non-volatile data blocks, and an erase inhibit flag in each information block coupled to the means for setting a predetermined maximum count value, the erase inhibit flag having one of a set condition and an unset condition for each block for preventing further erases to a block having its erase inhibit flag in the set condition.

11. The non-volatile semiconductor mass storage device according to claim 10 wherein the count value in each information block is represented by a plurality of bits programmed according to binary counting.

12. The non-volatile semiconductor mass storage device according to claim 10 wherein the count value and the erase inhibit flags are stored in a content addressable memory.

13. The non-volatile semiconductor mass storage device according to claim 10 further comprising a reset means for erasing all counters and all erase inhibit flags for every block at the maximum count value once insufficient blocks remain to store a pending data file.

14. The non-volatile semiconductor mass storage device according to claim 13 further comprising means for reading the mass storage comprising:

a. means for receiving the logical block address of a data file to be read;

b. means for selecting an appropriate physical address, coupled to the means for receiving the logical block address of the data file to be read, wherein the appropriate physical address correlates to the logical block address of the data file to be read; and

c. means for accessing the data file to be read from the appropriate physical address coupled to receive the physical address from the means for selecting an appropriate physical address.

15. The non-volatile semiconductor mass storage device according to claim 14 wherein the means for selecting an appropriate physical address comprises coupling the logical block address to a content addressable memory.