Flash memory mass storage architecture incorporating wear leveling technique without using cam cells
First Claim
1. A non-volatile semiconductor mass storage device comprising:
- a. a plurality of non-volatile data blocks, wherein each one of the plurality of non-volatile data blocks is selectively programmable and erasable and further wherein only those of the plurality of non-volatile data blocks that contain no data can be programmed;
b. a plurality of non-volatile information blocks for storing status information, each of said plurality of non-volatile information blocks directly corresponding to an appropriate one of the plurality of non-volatile data blocks, each of said plurality of non-volatile information blocks including a first flag which is indicative that a corresponding appropriate one of the plurality of non-volatile data blocks has been programmed, and further wherein an address of each one of a plurality of logical blocks corresponds to a physical address of the appropriate one of the plurality of non-volatile data blocks;
c. a comparator coupled to the plurality of non-volatile information blocks for determining whether any unprogrammed one of the plurality of non-volatile data blocks remain;
d. a controller coupled to the comparator for setting a first flag;
e. the controller for periodically erasing all of the plurality of non-volatile data blocks having first flags which are set;
f. a storage programmer for storing a logical block address associated with each one of the plurality of non-volatile data blocks within an appropriate one of the plurality of non-volatile information blocks forming a stored logical block address, whereby an erase cycle is not needed each time an updated block replaces a superseded data block; and
g. means for reading the non-volatile semiconductor mass storage device, comprising means for coupling a desired logical block address to the non-volatile semiconductor mass storage device and means for sequentially comparing the desired logical block address to each of the stored logical block addresses.
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Abstract
A semiconductor mass storage device can be substituted for a rotating hard disk. The device avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. Secondly, a circuit and method are provided for evenly using all blocks in the mass storage. These advantages are achieved through the use of several flags, a map to correlate a logical address of a block to a physical address of that block and a count register for each block. In particular, flags are provided for defective blocks, used blocks, old versions of a block, a count to determine the number of times a block has been erased and written and an erase inhibit flag. Reading is performed by providing the logical block address to the memory storage. The system sequentially compares the stored logical block addresses until it finds a match. That data file is then coupled to the system.
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Citations
15 Claims
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1. A non-volatile semiconductor mass storage device comprising:
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a. a plurality of non-volatile data blocks, wherein each one of the plurality of non-volatile data blocks is selectively programmable and erasable and further wherein only those of the plurality of non-volatile data blocks that contain no data can be programmed; b. a plurality of non-volatile information blocks for storing status information, each of said plurality of non-volatile information blocks directly corresponding to an appropriate one of the plurality of non-volatile data blocks, each of said plurality of non-volatile information blocks including a first flag which is indicative that a corresponding appropriate one of the plurality of non-volatile data blocks has been programmed, and further wherein an address of each one of a plurality of logical blocks corresponds to a physical address of the appropriate one of the plurality of non-volatile data blocks; c. a comparator coupled to the plurality of non-volatile information blocks for determining whether any unprogrammed one of the plurality of non-volatile data blocks remain; d. a controller coupled to the comparator for setting a first flag; e. the controller for periodically erasing all of the plurality of non-volatile data blocks having first flags which are set; f. a storage programmer for storing a logical block address associated with each one of the plurality of non-volatile data blocks within an appropriate one of the plurality of non-volatile information blocks forming a stored logical block address, whereby an erase cycle is not needed each time an updated block replaces a superseded data block; and g. means for reading the non-volatile semiconductor mass storage device, comprising means for coupling a desired logical block address to the non-volatile semiconductor mass storage device and means for sequentially comparing the desired logical block address to each of the stored logical block addresses. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification