System and method for real-time control of semiconductor a wafer polishing, and a polishing head
First Claim
1. A system for polishing a semiconductor wafer comprising:
- a wafer polishing assembly for polishing a face of a semiconductor wafer at a polishing rate and a polishing uniformity, the wafer polishing assembly including a platen rotatable about a first axis, a polishing head which supports the semiconductor wafer for rotation about a second axis, and a polishing head displacement mechanism which moves the polishing head and wafer across the platen, the wafer polishing assembly having a plurality of controllable operational parameters that upon variation change the polishing rate and polishing uniformity;
a controller operably coupled to the wafer polishing assembly for monitoring and managing in situ at least one of the operational parameters of the wafer polishing assembly;
a processor operably coupled to the controller for determining a set of desired operational parameters based on the monitored operational parameters and outputting control information indicative of the desired operational parameters to the controller; and
the controller adjusting in situ at least one of the operational parameters of the wafer polishing assembly in response to the control information from the processor to effectuate a new polishing rate and a new polishing uniformity as the wafer polishing assembly continues to polish the face of the semiconductor wafer.
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Abstract
A system for polishing a semiconductor wafer includes a rotatable platen subassembly and a drive mechanism coupled to rotate the platen subassembly at a platen velocity. A polishing head supports and holds a face of the semiconductor wafer in contact with the platen subassembly to polish the wafer face whereby individual regions of the wafer face have different polishing rates. The polishing head includes pressure applicators for applying various localized pressures on the individual regions of the semiconductor wafer to conform the wafer face to a selected contour. The system also includes a polish control subsystem for monitoring in situ the polishing rates at various regions of the semiconductor wafer. The polish control subsystem adjusts in situ the platen velocity and/or the individual localized pressures applied to the semiconductor wafer to change the polishing rates of the individual regions of the semiconductor wafer. The system can also be adapted to change other operational parameters, such as wafer velocity, wafer polishing path across the platen, slurry composition and flow rate (for CMP processes), and force applied to the wafer when contacting the platen. A method for polishing a semiconductor wafer is also described.
476 Citations
41 Claims
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1. A system for polishing a semiconductor wafer comprising:
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a wafer polishing assembly for polishing a face of a semiconductor wafer at a polishing rate and a polishing uniformity, the wafer polishing assembly including a platen rotatable about a first axis, a polishing head which supports the semiconductor wafer for rotation about a second axis, and a polishing head displacement mechanism which moves the polishing head and wafer across the platen, the wafer polishing assembly having a plurality of controllable operational parameters that upon variation change the polishing rate and polishing uniformity; a controller operably coupled to the wafer polishing assembly for monitoring and managing in situ at least one of the operational parameters of the wafer polishing assembly; a processor operably coupled to the controller for determining a set of desired operational parameters based on the monitored operational parameters and outputting control information indicative of the desired operational parameters to the controller; and the controller adjusting in situ at least one of the operational parameters of the wafer polishing assembly in response to the control information from the processor to effectuate a new polishing rate and a new polishing uniformity as the wafer polishing assembly continues to polish the face of the semiconductor wafer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A system for polishing a semiconductor wafer comprising:
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a rotatable platen subassembly defining a polishing area; a drive mechanism coupled to rotate the platen subassembly at a platen velocity; a polishing head for supporting a semiconductor wafer and holding a face of the semiconductor wafer in contact with the platen subassembly to polish the wafer face whereby individual regions of the wafer face have different polishing rates, the polishing head being movable across the platen subassembly; the polishing head having pressure applicators for applying various localized pressures on the individual regions of the semiconductor wafer to conform the wafer face to a selected contour; and a polish control subsystem for monitoring in situ the polishing rates at various regions of the semiconductor wafer, the polish control subsystem adjusting in situ the platen velocity, the individual localized pressures applied to the semiconductor wafer to change the polishing rates of the individual regions of the semiconductor wafer. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
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24. A polishing head for use in polishing a semiconductor wafer, the polishing head comprising:
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a rotatable wafer carrier including a recess sized to accommodate a semiconductor wafer, the semiconductor wafer having a non-exposed face juxtaposed with the wafer carrier and an exposed face to be polished; and a plurality of pressure applicators provided on the wafer carrier and in contact with the non-exposed face of the semiconductor wafer, the pressure applicators being controllable to apply isolated pressures to respective regions of the semiconductor wafer to cause alterations in contour of the exposed face of the semiconductor wafer. - View Dependent Claims (25, 26, 27)
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28. A method for polishing a semiconductor wafer comprising the following steps:
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providing a wafer polishing assembly for polishing a face of a semiconductor wafer at a polishing rate and a polishing uniformity, the wafer polishing assembly including a platen subassembly rotatable about a first axis, a polishing head which supports the semiconductor wafer for rotation about a second axis, and a polishing head displacement mechanism which moves the polishing head and wafer across the platen subassembly at an adjustable rate; using the wafer polishing assembly to polish a face of a semiconductor wafer at a polishing rate and a polishing uniformity according to a set of controllable operational parameters that upon variation change the polishing rate and polishing uniformity; monitoring in situ at least one of the operational parameters of the wafer polishing assembly; determining a set of desired operational parameters based upon the monitored operational parameters and outputting control information indicative of the desired operational parameters; and adjusting in situ at least one of the operational parameters in response to the control information to effectuate a new polishing rate and a new polishing uniformity and then continuing polishing of the semiconductor wafer face according to the new polishing rate and new polishing uniformity. - View Dependent Claims (29, 30, 31, 32, 33, 34)
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35. A method for polishing a semiconductor wafer comprising the following steps:
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polishing a face of a semiconductor wafer according to a set of controllable operational parameters which yields different polishing rates at various regions of the semiconductor wafer face using a polishing head including a rotatable wafer carrier including a recess sized to accommodate a semiconductor wafer, the semiconductor wafer having a non-exposed face juxtaposed with the wafer carrier and an exposed face to be polished and a plurality of pressure applicators on the wafer carrier and in contact with the non-exposed face of the semiconductor wafer, the pressure applicators being controllable to apply isolated pressure to respective regions of the semiconductor wafer to cause alterations in contour of the exposed face of the semiconductor wafer; monitoring in situ the polishing rates of the regions of the semiconductor wafer face; and adjusting in situ at least one operating parameter to change the polishing rates of at least one region. - View Dependent Claims (36, 37, 38)
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39. A polishing head for use in polishing a semiconductor wafer, the polishing head comprising:
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a wafer carrier sized to support a semiconductor wafer, the semiconductor wafer having a non-exposed face juxtaposed with the wafer carrier and an exposed face to be polished; and a plurality of pressure applicators provided on the wafer carrier and operative against the non-exposed face of the semiconductor wafer, the pressure applicators being controllable to apply isolated pressures to respective regions of the semiconductor wafer to cause alterations in contour of the exposed face of the semiconductor wafer.
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40. A system for polishing a semiconductor wafer comprising:
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a platen subassembly defining a polishing area; a polishing head for supporting a semiconductor wafer and holding a face of the semiconductor wafer in contact with the platen subassembly to polish the wafer face wherein individual regions of the wafer face have different polishing rates; the polishing head having pressure applicators for applying various localized pressures on the individual regions of the semiconductor wafer to conform the wafer face to a selected contour; and a polish control subsystem for monitoring in situ the polishing rates at various regions of the semiconductor wafer, the polish control subsystem adjusting in situ the individual localized pressures applied to the semiconductor wafer to change the polishing rates of the individual regions of the semiconductor wafer.
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41. A polishing head for use in polishing a semiconductor wafer, the polishing head comprising:
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a wafer carrier including means for supporting a semiconductor wafer, the semiconductor wafer having a non-exposed face juxtaposed with the wafer carrier and an exposed face to be polished; and means for causing alterations in contour of the exposed face of the semiconductor wafer.
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Specification