Trench EEPROM with tunnel oxide in trench

• US 5,486,714 A
• Filed: 05/22/1995
• Issued: 01/23/1996
• Est. Priority Date: 07/18/1994
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hong, Gary
• Primary Examiner(s): LARKINS, WILLIAM
• Application Number:
  US08/445,939
• Time in Patent Office: 246 Days
• Field of Search: 257/321, 257/322, 257/316, 257/330, 257/331, 257/332, 257/333, 257/334
• US Class Current: 257/321
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A floating gate EPROM has surface source and drain regions, with a trench between the source and drain regions containing the floating and control gates. A thin tunneling oxide layer is located at the bottom of the trench and on the sidewalls of the trench adjacent the source and drain regions, with thicker gate oxide elsewhere in the trench.

Claims

1. The Flash EEPROM memory comprising:

a stacked polysilicon gate structure in a trench within a semiconductor substrate and extending above said semiconductor substrate;

source and drain regions on either side of said stacked polysilicon gate structure at the surface of said substrate;

a thin tunnel oxide layer overlying said source and drain regions, on the sidewalls of the upper portions of said trench contacting said source and drain regions, and at a small center portion of the bottom of said trench;

a thick gate oxide layer on the sidewalls and bottom of said trench not covered by said thin tunnel oxide layer;

a polysilicon floating gate at the base of said stacked polysilicon gate structure;

an interpoly dielectric layer overlying said polysilicon floating gate; and

a polysilicon control gate overlying said interpoly dielectric layer.

2. The device of claim 1 wherein said tunnel oxide has a thickness of between about 60 to 100 Angstroms.

3. The device of claim 1 wherein said thick gate oxide layer is between about 200 to 300 Angstroms in thickness.

4. The device of claim 1 wherein said interpoly dielectric layer is composed of ONO (silicon oxide-silicon nitride-silicon oxide).

5. The Flash EEPROM memory comprising:

a polysilicon floating gate within a trench within a semiconductor substrate;

source and drain regions on either side of said floating gate at the surface of said substrate;

a thin tunnel oxide layer overlying said source and drain regions, on the sidewalls of the upper portions of said trench contacting said source and drain regions, and at a small center portion of the bottom of said trench;

a thick gate oxide layer on the sidewalls and bottom of said trench not covered by said thin tunnel oxide layer;

an interpoly dielectric layer overlying said polysilicon floating gate; and

a polysilicon control gate overlying said interpoly dielectric layer.

6. The device of claim 5 wherein said tunnel oxide has a thickness of between about 60 to 100 Angstroms.

7. The device of claim 5 wherein said thick gate oxide layer is between about 200 to 300 Angstroms in thickness.

8. The device of claim 5 wherein said interpoly dielectric layer is composed of ONO (silicon oxide-silicon nitride-silicon oxide).