Synchronizing signal separating apparatus and method

• US 5,486,869 A
• Filed: 12/13/1993
• Issued: 01/23/1996
• Est. Priority Date: 02/18/1992
• Status: Expired

• Current Assignee: Technology Licensing Corporation
• Original Assignee: J. Carl Cooper
• Inventors: Cooper, J. Carl
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): GRANT, CHRISTOPHER C
• Application Number:
  US08/165,688
• Time in Patent Office: 771 Days
• Field of Search: 348/525, 348/529, 348/530, 348/531, 348/521
• US Class Current: 348/525
• CPC Class Codes: H04N 5/08 Separation of synchronising signals from picture signals

Abstract

The present invention provides a synchronizing signal separation. In accordance with the present invention, a sync pulse processing circuitry slices a video signal and senses the peaks of the synchronizing pulse. A reference generating circuitry divides the output from the sync pulse processing circuitry into a plurality of reference signals that are compared with the video signal, thereby producing logic level outputs. A sync restoring circuitry combines the logic level outputs to provide precisely reconstructed synchronizing pulses of the video signal. The present invention incorporates different standard functions with superior performance because it may be applied for different types of video signals.

Claims

1. A video signal processing apparatus for use with the synchronizing pulses thereof, said synchronizing pulses having at least a leading edge and a trailing edge including in combination:

at least one sampling circuit for sampling said synchronizing pulses in response to a plurality of sampling signals to generate at least a first reference signal and a second reference signal, said reference signals respectively representing different levels of said synchronizing pulses, wherein said sampling circuit includes DC restoring for restoring said synchronizing pulses to a predetermined DC reference level which said DC restored synchronizing pulses are coupled to at least one comparing circuit for comparing said video signal with a level responding to said reference signals thereby providing at least a precision sliced pulse signal, with said sampling being independent of said precision sliced pulse signal.

2. A video signal processing apparatus as recited in claim 1 wherein said sampling circuit further comprises:

a detecting circuit for detecting respective levels of said synchronizing pulses in response to said leading and trailing edges and outputting a first level signal and a second level signal; and

converting circuit for converting said first and second level signals into said first and second reference signals.

3. A video signal processing apparatus as recited in claim 2 wherein said first reference signal represents a middle level value of said synchronizing pulse, said second reference signal represents a level value above said middle level value, said sampling means further generates a third reference signal representing a level value below said middle level value.

4. A video signal processing apparatus for use with synchronizing pulses of a video signal including:

at least one sampling circuit for sampling said synchronizing pulses in response to a plurality of sampling signals provided , in response to said synchronizing pulses to generate at least a first reference signal and a second reference signal, said reference signals respectively representing different levels of said synchronizing pulses; and

comparing circuit for comparing said synchronizing pulses with a level responding to said reference signals to generate precision sliced pulses, with said sampling being independent of said precision sliced pulses, and further comprising combining said precision sliced pulses to generate horizontal rate and vertical rate pulse signals.

5. A video signal processing apparatus as recited in claim 4 wherein said combining comprises filtering for filtering one of said precision sliced pulse signals to generate said vertical rate pulse signal.

6. A synchronous signal processing apparatus for a video signal comprising:

slicing means for slicing said video signal to generate sliced pulses, said sliced pulses corresponding to respective synchronous pulses of said video signal, each of said sliced pulses having a leading edge and a trailing edge;

level detecting means for detecting respective levels of said synchronous pulses of said video signal in response to said leading and trailing edges and providing a first level signal in response to one of said edges and a second level signal in response to the other of said edges; and

sync restoring means for detecting different levels of said synchronous pulses in response to said first and second level signals and generating a derived sync pulse output in response thereto.

7. A synchronous signal processing apparatus as recited in claim 6 wherein said sync restoring means comprises:

transforming means for transforming said first and second level signals into a first reference signal, a second reference signal and a third reference signal; and

comparing means for comparing said synchronous pulses with said first, second and third reference signals to generate logic level outputs.

8. A synchronous signal processing apparatus as recited in claim 7 wherein said sync restoring means further comprises means for filtering said derived sync pulse output to generate a vertical synchronous output.

9. A synchronous signal processing apparatus as recited in claim 8 wherein said filter means operates in response to a frequency ranging from 0-10 KHz.

10. A synchronous signal processing apparatus as recited in claim 6 further comprising format selecting means for selecting the format of said video signal being processed.

11. A synchronous signal processing apparatus as recited in claim 6 wherein said first and second level signals respectively represent a positive peak value and a negative peak value of said synchronous pulses.

12. A synchronous signal processing apparatus as recited in claim 8 wherein said filter means substantially operates to pass frequencies ranging from 0-1 KHz with less than 50% normalized amplitude attenuation, and having at least 90% normalized amplitude attenuation at frequencies greater than 10 KHz said normalized attenuations with respect to the level of DC response at the output.

13. A video signal processing apparatus, said video signal having synchronous pulses of a pulse amplitude, said apparatus comprising:

sync tip clamping means for clamping said video signal to provide a clamped pulse signal, respective pulse of said clamped pulse signal having a leading edge and a trailing edge;

peak detecting means for sampling said video signal in response to said leading and trailing edges to generate a positive peak signal and a negative peak signal;

level dividing means for dividing level between said positive and negative peak signals into a first reference level, a second reference level and a third reference level; and

comparing means for comparing said video signal with respective said reference levels to generate logic level outputs.

14. A video signal processing apparatus as recited in claim 13 wherein said first reference level represents a mean value of said pulse amplitude, said second reference level represents a upper value and said third reference level represents a lower value.

15. A video signal processing apparatus as recited in claim 14 wherein said upper value is a sum of said mean value and an offset value, said lower value is a difference of said mean value and said offset value.

16. A video signal processing apparatus as recited in claim 15 wherein said offset value is one half of the value between said mean value and said positive peak.

17. A video signal processing apparatus, said video signal having synchronous pulses of a pulse amplitude, said apparatus comprising:

format selecting means responsive to the format of said video signal for determining the format of said video signal being processed;

sync tip clamping means for clamping respective sync tips of said video signal to provide a clamped pulse signal corresponding to said synchronous pulses, each respective pulse of said clamped pulse signal having a leading edge and a trailing edge;

sync slicing means coupling to said sync tip clamping means, for limiting an amplitude of said clamped pulse signal to provide a coarse sliced sync signal;

peak detecting means for sampling positive and negative peaks respectively of said synchronous pulses of said video signal in response to said leading and trailing edges, thereby generating a positive peak signal and a negative peak signal;

level dividing means for dividing level between said positive and negative peak signals into a first reference level, a second reference level and a third reference level, said first, second and third reference levels respectively representing different portion levels of said pulse amplitude;

comparing means for comparing said video signal with respective said reference levels to generate logic level outputs; and

restoring means coupling to said comparing means, for combining said logic level outputs to generate a plurality of precision synchronous outputs.

18. A video signal processing apparatus as recited in claim 17 wherein said first reference level represents a mean value of said pulse amplitude, said second reference level represents a level value above said mean value and said third reference level represents a value below said mean value.

19. A method for processing a synchronous signal of a video signal comprising steps of:

slicing said video signal to generate a sliced sync pulse signal;

sampling said video signal in response to respective leading edges and trailing edges of said sliced pulse signal so as to generate a first sample level signal and a second sample level signal;

converting said first and second sample level signals into a first reference signal, a second reference signal and a third reference signal, said first reference signal representing a middle level of each synchronous pulse of said video signal, said second reference signal representing a upper level above said middle level and said third reference signal representing a lower level below said middle level;

comparing said respective reference signals with said video signal to generate logic level outputs; and

restoring desired synchronous pulses in response to said logic level outputs.

20. A video signal processing apparatus as recited in claim 19 wherein said method further comprises a step of adjusting a pulse width of said sliced sync pulse signal in response to a format selecting signal generated by a mode selecting switch.

21. A method of generating an output sync signal corresponding to the sync portion of a composite video signal which sync portion comprises a plurality of sync levels, one of which said sync levels includes blanking level, said method including the steps of:

a. generating a plurality of level signals having magnitudes responsive to said sync levels,

b. establishing at least one reference level between each of said sync levels in response to said level signals, the number thereof changeable in response to the number of said sync levels,

c. for each said reference level established, generating a binary pulse version of said sync portion by comparison of said reference levels and said sync portion,

d. generating said output sync signal in response to said binary pulse versions of step c.

23. A method as claimed in claim 21 or 22 wherein said sync portion takes on three or more levels including the blanking level and two or more reference levels are established such that their values lie substantially equidistant from the outer level signals.

24. A method as claimed in claim 21 or 22 wherein, said comparison of said reference levels and said sync portion provides time sequential binary pulse versions as said sync portion transcends said reference levels.

25. A method as claimed in claim 21 or 22 wherein said binary pulse versions are time sequential and are combined so that a first edge of said output sync signal occurs in response to a first said binary pulse version, and a second edge of said output sync signal occurs in response to a second said binary pulse version.

26. A method as claimed in claim 21 or 22 including the step of determining if said composite video signal is a HDTV type video signal, and modifying said reference levels in response thereto.

22. A method of generating an output sync signal corresponding to the sync portion of a composite video signal which sync portion comprises a plurality of sync tip levels and a blanking level, said method including:

a. generating a plurality of level signals having magnitudes responsive to said sync tip levels,

b. establishing a plurality of reference levels between said sync tip levels in response to said level signals,

c. generating a plurality of binary pulse versions of said sync portion by comparison of said reference levels and said sync portion,

d. combining said plurality of binary pulse versions to generate said output sync signal.

27. An apparatus for deriving a logic level version of the sync portion of a video type signal, said sync portion having a plurality of levels, one of which may be a blanking level, said apparatus including:

circuitry responsive to said sync portion to clamp the sync tip thereof to a known level thereby providing a clamped sync portion and to generate at least a first logic level sync signal in response to said clamped sync portion;

circuitry for clamping said sync portion to a known level to provide a second clamped sync portion;

circuitry for providing at least one reference signal in response to said first logic level sync signal and said second clamped sync portion;

circuitry for comparing said second clamped sync portion to said reference signal to provide said logic level version.

28. An apparatus as claimed in claim 27 wherein in said circuitry for clamping the sync tip to a known level, said known level is established by one or more semiconductor junction voltage drops.

29. An apparatus as claimed in claim 27 or 28 wherein one said reference signal is responsive to the level of the blanking level of said second clamped sync portion.

30. An apparatus as claimed in claim 27 or 28 wherein one said reference signal is responsive to the sync tip level of said second clamped sync portion.

31. An apparatus for deriving a logic level version of the sync portion of a video type signal, said sync portion having a number of levels N, one of which may be a blanking level, and where N may be two or more depending on the format of said video type signal, said apparatus including:

circuitry to provide a format signal changeable in response to the format of said video type signal;

circuitry responsive to said sync portion to generate at least a first separated sync signal;

circuitry for providing at least N-1 reference signal(s) in response to said sync portion and said first separated sync signal; and

circuitry responsive to said sync portion and said format signal and said reference signal(s) for comparing said sync portion to said reference signal(s) to provide said logic level version.

32. An apparatus as claimed in claim 31 wherein one said reference signal is responsive to the level of said sync portion which has the level closest to the peak white value of said video type signal.

33. An apparatus as claimed in claim 31 wherein said circuitry to provide a format signal is responsive to said video type signal to change said format signal in response thereto.

34. An apparatus as claimed in claim 31, 32 or 33 wherein N is two for NTSC or PAL type video signals and N is 3 for HDTV type video signals and where one said reference signal is provided for NTSC or PAL type video signals and at least two said reference signals are provided for HDTV type video signals, each which reference signals are responsive to at least one sync portion level.

35. A video sync pulse circuit responsive to composite sync pulses which may be part of a composite video signal said circuit operative to provide a reference voltage corresponding to the 50% level of sync, including in combination:

a) a coupling capacitor coupled to an input terminal to AC couple said composite sync pulses to a sync tip clamp circuit, said sync tip clamp circuit including a source of current operative to charge said coupling capacitor in a first direction and further including circuitry to charge said coupling capacitor in the opposite direction during at least a portion of the time said AC coupled sync tips surpass a reference, said charging action thus providing sync tip clamping to provide a sync tip clamped signal;

b) a buffer, responsive to said sync tip clamped signal to buffer same to provide a buffered signal;

c) a comparator responsive to said buffered signal and a reference to provide a compared sync signal;

d) a plurality of pulse circuits responsive to said compared sync signal from said comparator to provide a first sample and hold pulse in response to the leading edge of said compared sync signal and a second sample and hold pulse in response to the trailing edge of said compared sync signal;

e) a first sample and hold circuit responsive to said first sample and hold pulse and a DC restored form of said composite sync pulses to sample and hold the voltage level of sync tip;

f) a second sample and hold circuit responsive to said second sample and hold pulse and blanking level of said DC restored form of said composite sync pulses to sample and hold the voltage level of blanking;

g) a divider circuit responsive to the held voltage of sync tip and the held voltage of blanking to provide an in between voltage which is said reference voltage;

wherein circuitry used to accomplish one of elements a) through g) may be shared between two or more elements.

37. The video sync pulse circuit of claim 35 or 36 wherein element b) includes amplification, in element e) said first sample and hold pulse is delayed with respect to the leading edge of sync tip to allow said first sample and hold pulse to start within said sync tip and in element c) said buffered signal has reduced high frequency components as compared to said sync tip clamped signal of a).

38. The video sync pulse circuit of claim 35 or 36 wherein said comparator of element c) includes adjustment of the magnitude of the difference between said buffered signal and said reference value which adjustment is made in relation to the sync level of said buffered video to provide a reduction in comparator sensitivity to noise.

36. A video sync pulse separator circuit responsive to a composite video signal for providing horizontal and vertical sync pulses including in combination:

a) a coupling capacitor to AC couple said composite video signal to a sync tip clamp circuit, said sync tip clamp circuit including a source of current operative to charge said coupling capacitor in a first direction and further including circuitry to charge said coupling capacitor in the opposite direction during at least a portion of the time any AC coupled sync tip surpasses a reference, said charging action thus sync tip clamping to provide a sync tip clamped signal;

b) a buffer responsive to said sync tip clamped video signal to buffer said sync tip clamped video to provide a buffered signal;

c) a comparator responsive to said buffered signal and a reference to provide a compared sync signal;

d) a plurality of pulse circuits responsive to said compared sync signal from said comparator to provide a first sample and hold pulse in response to the leading edge of said compared sync signal and a second sample and hold pulse in response to the trailing edge of said compared sync signal;

e) a first sample and hold circuit responsive to said first sample and hold pulse and sync tip of a DC restored form of said composite video signal to sample and hold the voltage level of sync tip;

f) a second sample and hold circuit responsive to said second sample and hold pulse and blanking level of said DC restored form of said composite video signal to sample and hold the voltage level of blanking;

g) a divider circuit responsive to the held voltage of sync tip and the held voltage of blanking to provide an in between reference voltage;

h) a further comparator responsive to said reference voltage and comparison video to provide reference sync pulses, said comparison video being a version of said composite video signal of element a) having a known DC level;

i) a half horizontal pulse eliminator circuit responsive to said reference sync pulses to output horizontal rate pulses;

j) a vertical synchronizing filter circuit responsive to said reference sync pulses to output a vertical rate pulse;

k) a field synchronizing circuit responsive to at least circuit element j) and to the relationship of horizontal sync pulses and the leading edge of vertical sync to output a field synchronizing pulse signifying odd and even fields,

wherein circuitry used to accomplish one of elements a) through k) may be shared between a plurality of elements.

39. A method for processing a sync portion of a video type signal, said sync portion having a plurality of levels, comprising steps to:

a) a first separation of said sync portion to generate a first separated sync signal, including clamping the sync tip of said sync portion to a known level before said first separation;

b) generating a plurality of level signals each being representative of a level of a second clamping of said sync portion, at least one of said level signals is also generated in response to said first separated sync signal;

c) providing a reference signal in response to said plurality of level signals;

d) a second separation of said second clamped sync portion in response to said reference signal to provide a second separated sync signal which is a version of said sync portion.

41. A method as claimed in claim 39 or 40 wherein said step b) includes establishing one level of said sync portion at a known level in response to said first separated sync signal before said generating and with step d) performed on said second clamped sync portion having one level established of step b).

40. A method for processing a sync portion of a video type signal, said sync portion having a plurality of levels, comprising steps to:

a) a first separation of said sync portion to generate a first separated sync signal, including clamping the sync tip of said sync portion to a known level established by one or more semiconductor junction voltage drops before said first separation;

b) generating a plurality of level signals each being representative of a level of a second clamping of said sync portion, at least one of said level signals is also generated in response to said first separated sync signal;

c) providing a reference signal in response to said plurality of level signals;

d) a second separation of said second clamped sync portion in response to said reference signal to provide a second separated sync signal which is a version of said sync portion.