Structure and method for low current programming of flash EEPROMS

• US 5,487,033 A
• Filed: 06/28/1994
• Issued: 01/23/1996
• Est. Priority Date: 06/28/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Keeney, Stephen N., Atwood, Gregory E.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): LE, VU ANH
• Application Number:
  US08/267,815
• Time in Patent Office: 574 Days
• Field of Search: 365/185, 365/218, 365/184, 365/189.01, 365/104
• US Class Current: 365/185.19
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5622 Concurrent multilevel programming of more than one cell
• CPC Class Codes: G11C 2211/565 Multilevel memory comprising elements in triple well structure
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A system and method for programming non-volatile memory enables fast low current programming. Low current programming is achieved by applying a source bias voltage and increasing the drain voltage to be greater than the source bias voltage to maintain fast programming. Furthermore, the control gate voltage may be stepped or ramped from a minimum value to a maximum value to further reduce the peak channel current and to allow the flash cell threshold voltage to be placed to an exact value, for MLC applications. Ramping or stepping of the control gate may be done independently or in conjunction with an applied source bias voltage. Furthermore, the reduced cell current allows more cells to be programmed in parallel which improves program performance and the drain select device can be reduced in size to reduce die area.

Claims

1. A low current method for programming a cell of an electrically erasable programmable read only memory (EEPROM), said EEPROM comprising at least one cell, each cell having a floating gate, a control gate, a source junction and drain junction, said method comprising the steps of:

applying a source bias voltage to the source junction of the cell;

applying an initial gate voltage to the control gate of the cell, and stepping the control gate voltage in predetermined increments to a maximum gate voltage; and

applying a drain voltage pulse to the drain junction of the cell to cause hot electron injection of electrons onto the floating gate, said drain voltage pulse applied at each stepped increment of the control gate voltage.

2. The low current method for programming as set forth in claim 1, wherein the predetermined increments is approximately equal to 100 mV.

3. The low current method for programming as set forth in claim 1, wherein the step of applying a source bias voltage applies a voltage of 0 volts.

4. The low current method for programming as set forth in claim 1, wherein a plurality of drain voltage pulses are applied at each stepped increment of the control gate voltage.

5. The low current method for programming as set forth in claim 1, wherein the step of applying a drain voltage further comprises the step of pulsing the drain voltage a determined number of times to cause a threshold voltage of the cell to be a predetermined value.

6. The low current method as set forth is claim 1, wherein the EEPROM is a flash EEPROM.

7. The low current method as set forth is claim 1, wherein each cell stores one of a plurality of states by storing a discrete amount of charge on the floating gate.

8. A low current method for programming a cell of an electrically erasable programmable read only memory (EEPROM), said EEPROM comprising at least one cell, each cell having a floating gate, a control gate, a source junction and drain junction, said method comprising the steps of:

placing the cells in a first well which is contained in a second well in a substrate;

applying a gate voltage to the control gate of the cell;

applying a drain voltage to the drain junction of the cell, said drain voltage set to cause hot electron injection of electrons onto the floating gate;

applying a first well bias voltage to the first well, the first well bias voltage to eliminate the need for applying a source bias voltage; and

applying a second well bias voltage to the second well.

9. The low current method for programming as set forth in claim 8, wherein the substrate is a p-substrate, the first well is a p-well and the second well is an n-well;

the step of applying the first well bias voltage to the first well comprises applying a negative bias voltage of an amount to eliminate the need for applying a source bias voltage; and

the step of applying a second well bias voltage to the second well comprises the step of applying a positive voltage to isolate the first well.

10. A memory device comprising:

a memory array comprising a plurality of cells, each cell comprising a floating gate, control gate, source junction and drain junction; and

programming circuitry for programming a cell by applying an initial gate voltage to the control gate of the cell, and stepping the control gate voltage in predetermined increments to a maximum gate voltage, applying a source bias voltage to the source junction of the cell, and applying a drain voltage pulse to the drain junction of the cell to cause hot electron injection of electrons onto the floating gate, said drain voltage pulse applied at each stepped increment of the control gate voltage.

11. The memory device as set forth in claim 10, wherein said programming circuitry further comprises at least one source bias resistor coupled to the source junction to provide the source bias voltage to the source junction.

12. The memory device as set forth in claim 10, wherein said programming circuitry further comprises a plurality of source bias resistors, one source bias resistor coupled to each source junction of each cell.

13. The memory device as set forth in claim 10, wherein said programming circuitry further comprises a plurality of source resistors, one source resistor coupled to a group of cells, wherein when a cell of a group is programmed, the source resistor provides the source bias voltage to the source junction.

14. The memory device as set forth in claim 10, wherein said programming circuitry programs a plurality of cells in parallel.

15. The memory device as set forth in claim 10, wherein said memory device further comprises at least one well, at least one cell located within the at least one well, said programming circuitry applying a negative well bias voltage to the well and applying approximately a zero source bias voltage to the source junction of the cell located within the well.

16. The memory device as set forth in claim 10, wherein the cell is a multilevel cell.

17. The memory device as set forth in claim 10, wherein the cell is a flash EEPROM cell.

18. A memory device comprising:

memory array means comprising a plurality of cells, each cell comprising a floating gate, control gate, source junction and drain junction; and

means for applying a source bias voltage to the source junction of the cell;

means for applying an initial gate voltage to the control gate of the cell, said means for stepping the control gate voltage in predetermined increments to a maximum gate voltage; and

means for applying a drain voltage pulse to the drain junction of the cell at each stepped increment of the control gate voltage, said means causing hot electron injection of electrons onto the floating gate.