Host selectively determines whether a task should be performed by digital signal processor or DMA controller according to processing time and I/O data period

• US 5,487,154 A
• Filed: 07/14/1992
• Issued: 01/23/1996
• Est. Priority Date: 07/18/1991
• Status: Expired due to Term

• Current Assignee: Advantest Corporation
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Gunji, Keita
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Luu, Le Hien
• Application Number:
  US07/913,608
• Time in Patent Office: 1,288 Days
• Field of Search: 395/250, 395/275, 395/425, 395/650, 395/700, 395/800, 364/200
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A low-cost digital signal processing system is provided which can prevent data loss during data transfer and can eliminate processing overhead regardless of the length of the I/O period of an external I/O processing device. When the data I/O period of the external I/O device such as an A/D converter is shorter than the period of data processing by the DSP, the data reception and transmission are performed through a DMA controller between the external I/O devices and the memory to reduce the burden on the DSP. On the other hand, when the data input and output period is longer than the DSP processing time, the data reception and transmission is directly carried out by the external I/O device and the DSP without use of the DMA controller. In addition, in the execution of a DSP program which comprises at least one process, a function of each process is provided to have input and output parameters identifying the addresses of data reception or transmission units which are assigned to the input and output parameters to simplify the DSP programming.

Claims

1. A signal processing apparatus comprising:

memory means for storing digital signals and processes for processing said digital signals;

input and output (I/O) means for inputting and outputting said digital signals to and from said signal processing apparatus;

a direct memory access (DMA) controller connected to said memory means and said I/O means for storing/reading said digital signals to/from said memory means and said I/O means in a direct memory access mode;

a digital signal processor (DSP) connected to said DMA controller, said I/O means, and said memory means for processing said digital signals stored in said memory means, said DSP executing a data empty check program under the control of a real-time monitor including a semaphore for checking for the existence of said digital signals to be processed and executing another process when said digital signals are not available for processing; and

a host CPU connected to said DMA and said DSP for determining whether a data transfer requested by a task of said processes is performed by said DMA controller or said DSP based upon a comparison between an I/O data period and a processing time of said task, whereby said data transfer requested by said task is performed by said DMA when said I/O period is shorter than said processing time of said task.

2. Apparatus according to claim 1 wherein said DSP uses an interrupt for initiating data transfer with said I/O means when said processing time of said task is shorter than said I/O period.

3. Apparatus according to claim 1 wherein address of said I/O means are passed between said processes as input and output parameters in a process function call.

4. A method of processing digital signals in a signal processing apparatus comprising an input and output (I/O) means, memory means for storing said digital signals and a plurality of processes which operate on said digital signals, a direct memory access (DMA) controller, and a digital signal processor (DSP) for processing said digital signals stored in said memory means for digital signals received directly from said I/O means in accordance with a data transfer request from said plurality of processes, said method comprising the steps of:

a) executing a data empty check program on said DSP using a real-time monitor including a semaphore for checking for the existence of said digital signals to be processed and executing another process when said digital signals are not available for processing;

b) determining a processing period of a task processing said digital signals;

c) determining an I/O period;

d) comparing said processing period to said I/O period;

e) invoking said DMA controller for transferring said digital signals to/from said memory means based upon said comparison in step c) when said processing period is longer than said I/O period;

f) interrupting said DSP currently processing said digital signals based upon said comparison in step c) to initiate an I/O data transfer when said processing period is shorter than said I/O period; and

g) continuing processing of said digital signals in accordance with said plurality of processes stored in said memory means.

5. Method according to claim 5 comprising the further step of passing addresses of said I/O means between said processes as input and output parameters in a process function call.