Method of fabricating sidewall charge-coupled device with trench isolation

• US 5,488,010 A
• Filed: 05/10/1994
• Issued: 01/30/1996
• Est. Priority Date: 02/08/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Wong, Hon-Sum P.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): BILODEAU, THOMA
• Application Number:
  US08/241,137
• Time in Patent Office: 630 Days
• Field of Search: 437/53, 437/50, 437/67, 257/224
• US Class Current: 438/75
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 27/14812 Special geometry or disposition of pixel-elements, address lines or gate-electrodes
• CPC Class Codes: H01L 27/14831 Area CCD imagers
• CPC Class Codes: H01L 27/14856 Time-delay and integration

Abstract

A charge-coupled imaging device comprising a plurality of trenches in the surface of the silicon substrate which separate adjacent columns in the CCD device. A plurality of surface electrodes are provided on the surface of the charge-coupled device extending perpendicular to the isolation trenches, which electrodes provide for clocked transfer of charges between adjacent cells within each column of the charge-coupled device. The CCD cells are formed on the silicon ridges delineated between the isolation trenches, and this structure maximizes the three dimensional surface area of the CCD cells and facilitates transport of charges along the CCD cell sidewalls. The sidewall CCD with trench isolation provides a CCD cell layout size the same as that of a conventional two dimensional CCD cell, but with an increased charge capacity per CCD cell because of the larger three dimensional areas of the CCD cells. The increase in charge capacity means a larger signal-to-noise ratio and consequently a larger dynamic range. In one embodiment, a plurality of shallow electrodes are defined under the surface electrodes to increase the charge carrying surface area and provide better gate control.

Claims

1. A method of fabricating a sidewall charge-coupled device with trench isolation comprising the steps of:

providing a substrate of semiconductor material;

defining a plurality of isolation trenches in a surface of said substrate to form columns of charge coupled cells between the isolation trenches, said plurality of isolation trenches being formed to increase the surface areas of the charge coupled cells therebetween and facilitate transport of charges along the cell sidewalls;

disposing a plurality of alternating first and second sets of substantially parallel surface electrodes arranged in an overlapping electrode configuration over substantially the entire upper surface of the substrate extending substantially perpendicular to the isolation trenches, said plurality of alternating first and second sets of surface electrodes producing, by an applied electric field, an induced potential well in the substrate beneath each of the plurality of alternating first and second sets of surface electrodes, such that substantially the entire upper surface of the substrate and the sidewalls in common with the upper portions of the sidewalls of the isolation trenches produce photon to electron conversion in response to incident light; and

disposing a plurality of shallow trenches, shallow relative to the deeper isolation trenches, under the surface electrodes in each column of cells defined between adjacent isolation trenches to increase the charge carrying surface area and provide better gate control.

2. A method as claimed in claim 1, wherein said plurality of alternating first and second sets of surface electrodes comprise a storage electrode and a receiving electrode as adjacent surface electrodes and a transfer electrode and a blocking electrode as adjacent surface electrodes.

3. A method as claimed in claim 1, further including the step of disposing an insulation layer between said alternating first and second sets of surface electrodes and between said surface electrodes and said substrate.

4. A method as claimed in claim 1, wherein each of said plurality of isolation trenches is defined by etching a plurality of trenches in said substrate and wherein said isolation trenches are disposed by partially refilling said trenches with an undoped polysilicon semiconductor material to a depth S below the surface of the substrate, and forming a charge carrying sidewall of the trench to a depth S below the substrate.