Method of making an interconnect structure with an integrated low density dielectric

• US 5,488,015 A
• Filed: 05/20/1994
• Issued: 01/30/1996
• Est. Priority Date: 05/20/1994
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Jeng, Shin-Puu, Cho, Chih-Chen, Havemann, Robert H., Gnade, Bruce E.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Radomsky, Leon
• Application Number:
  US08/246,432
• Time in Patent Office: 620 Days
• Field of Search: 437/235, 437/238, 437/978, 437/231, 437/195, 148/DIG. 43, 148/DIG. 117, 148/DIG. 118
• US Class Current: 438/624
• CPC Class Codes: H01L 21/02123 the material containing silicon
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02203 the layer being porous
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/02359 treatment to change the surface groups of the insulating layer
• CPC Class Codes: H01L 21/02362 formation of intermediate layers, e.g. capping layers or diffusion barriers
• CPC Class Codes: H01L 21/31695 Deposition of porous oxides or porous glassy oxides or oxide based porous glass
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 2221/1047 the air gaps being formed by pores in the dielectric
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/043 Dual dielectric
• CPC Class Codes: Y10S 148/118 Oxide films

Abstract

This invention provides a semiconductor device and process for making the same with dramatically reduced capacitance between adjacent conductors and an interlayer dielectric construction which emphasizes mechanical strength, etch compatibility, and good heat transfer. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric and provide mechanical strength, heat transfer, and a solid layer for via etch. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Claims

1. A method of constructing a semiconductor device comprising:

providing a layer of patterned conductors formed on a semiconductor substrate;

depositing and gelling a layer of a precursor solution on said substrate, thereby forming a wet gel layer having porous structure;

drying said wet gel layer without substantial densification of said porous structure, thereby forming a porous dielectric layer filling gaps between and covering said patterned conductors, said porous dielectric layer having a dielectric constant of less than 3.0, a porosity between 30% and 95%, and an average pore diameter of less than 80 nm;

removing a top portion of said porous dielectric layer; and

depositing a non-porous dielectric layer over said conductors and said porous dielectric layer to complete an interlayer dielectric, whereby the capacitive coupling between conductors on the same level is substantially reduced compared to a solid silicon dioxide dielectric and the mechanical properties of said interlayer dielectric are essentially the same as that of non-porous silicon dioxide.

2. The method of claim 1, further comprising creating one or more metal-filled vias passing through said non-porous dielectric layer to provide electrical contact to said patterned conductors and forming a second layer of conductors over said non-porous dielectric layer.

3. The method of claim 1, further comprising surface treating said wet gel to render said wet gel hydrophobic prior to said drying said wet gel step.

4. The method of claim 1, further comprising before said porous dielectric forming step, conformally applying a passivation layer to said conductors.

5. The method of claim 1, wherein said step of depositing a non-porous dielectric layer comprises depositing bottom and top sublayers, said bottom sublayer deposited conformally and said top sublayer being a planarized layer.

6. The method of claim 5, wherein said bottom sublayer is deposited by a chemical vapor deposition process.

7. The method of claim 1, wherein said removing a top portion of said porous dielectric layer step comprises mechanically polishing said semiconductor device.

8. The method of claim 1, wherein said removing a top portion of said porous dielectric layer step exposes the tops of said conductors.

9. The method of claim 1, wherein said non-porous dielectric layer comprises the majority of said interlayer dielectric.