Layout for radio frequency power transistors

• US 5,488,252 A
• Filed: 08/16/1994
• Issued: 01/30/1996
• Est. Priority Date: 08/16/1994
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Johansson, Ted, Leighton, Larry, Hamberg, Ivar
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US08/291,427
• Time in Patent Office: 532 Days
• Field of Search: 257/578, 257/579, 257/584, 257/587
• US Class Current: 257/579
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/30111 matching

Abstract

A layout is provided for RF power transistors that reduces common lead inductance and its associated performance penalties. An RF transistor cell is rotated 90° with respect to a conventional RF transistor cell so as to located bond pads nearer the edge of a silicon die, reducing bond wire length and common lead inductance and thereby improving performance at high frequencies. The placement of bond pad and distribution of different parts of the transistor layout further reduces common lead inductance.

Claims

1. An RF power transistor comprising:

a silicon die;

a pair of interdigitated electrodes formed on the silicon die, each electrode having a multiplicity of parallel electrode fingers and each including at least one bond pad;

regions of a first type of diffusion formed beneath electrode fingers of one electrode of the pair of interdigitated electrodes, and regions of a second type of diffusion formed beneath electrode fingers of another electrode of the pair of interdigitated electrodes;

a first wire connected to a bond pad of said one electrode and extending in a direction predominantly parallel to the electrode fingers of the one electrode;

and a second wire connected to a bond pad of said another electrode and extending in a direction predominantly parallel to the electrode fingers of said another electrode;

wherein the silicon die is substantially rectangular and has a least dimension in a direction substantially parallel to the electrode fingers of the pair of interdigitated electrodes, and wherein at least one of the pair interdigitated electrodes includes a plurality of bonds pads, the apparatus further comprising at least one additional wire such that one wire is connected to each of said bond pads of each electrode.

2. The apparatus of claim 1, wherein all of the wires are substantially parallel.

3. The apparatus of claim 1, wherein the plurality of bond pads of said one electrode are spaced apart at substantially equal intervals.

4. The apparatus of claim 3, wherein each bond pad of said another electrode is located substantially in the center of one of said intervals.

5. An RF power transistor comprising:

a substrate;

a collector lead formed at one side of the substrate and a base lead formed at an opposite side of the substrate;

a silicon die;

a pair of interdigitated electrodes formed on the silicon die, each electrode having a multiplicity of parallel electrode fingers extending in substantially a same direction as a direction between the collector lead to the base lead, each electrode including at least one bond pad; and

regions of a first type of diffusion formed beneath electrode fingers of one electrode of the pair of interdigitated electrodes, and regions of a second type of diffusion formed beneath electrode fingers of another electrode of the pair of interdigitated electrodes; and

a first wire connected to a bond pad of said one electrode and extending in said same direction; and

a second wire connected to a bond pad of said another electrode and extending in said same direction;

wherein the silicon die is substantially rectangular and has a least dimension in a direction substantially parallel to the electrode fingers of the pair of interdigitated electrodes, and wherein at least one of the pair of interdigitated electrodes includes a plurality of bond pads, the apparatus further comprising at least one additional wire such that one wire is connected to each of said bond pads of each electrode.

6. The apparatus of claim 5, wherein all of the wires are substantially parallel.

7. The apparatus of claim 5, wherein the plurality of bond pads of said one electrode are spaced apart at substantially equal intervals.

8. The apparatus of claim 7, wherein each bond pad of said another electrode is located substantially in the center of one of said intervals.