Latch interface for self-reset logic

• US 5,488,319 A
• Filed: 08/18/1994
• Issued: 01/30/1996
• Est. Priority Date: 08/18/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lo, Tin-chee
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): DRISCOLL, BENJAMIN
• Application Number:
  US08/292,673
• Time in Patent Office: 530 Days
• Field of Search: 326/62, 326/95, 326/97, 326/98, 326/115, 326/121, 327/142
• US Class Current: 326/115
• CPC Class Codes: H03K 3/037 Bistable circuits

Abstract

A latch, connected between an input self-reset dynamic MOS logic circuit and an output self-reset dynamic MOS logic circuit, is provided with clocked interface circuitry to assure proper latching of the state of the input logic in the latch and provides a pulsed output to the output logic circuit. Circuitry is provided to control the self-reset operation of the input logic circuit such that the reset does not occur until a predetermined period of time after the leading edge of the clock pulse latching the state of the input self-reset circuit in the latch. The output of the latch is gated from the latch to the output self-reset circuit under the control of a chopper circuit. The chopper circuit provides a control pulse to gate the state of the latch to the output self-reset circuit a predetermined period of time after the data has been latched. The control pulse has a duration sufficient to assure that the state of the latch is registered in the output self-reset logic.

Claims

1. In combination, a logic circuit having an output terminal and including a logic tree and a reset circuit operative to reset the logic tree and a latch having an input terminal connected to the output terminal of the logic circuit, the latch responsive to a clock signal for periodically latching the output of the logic circuit, the reset circuit connected to the output terminal of the logic circuit and to the input terminal of the latch and responsive to a signal on the input terminal of the latch and the clock signal to reset the logic tree.

2. The combination in accordance with claim 1 wherein the logic tree comprises dynamic MOS logic circuits and the reset circuit is operative to charge circuit nodes of the logic tree.

3. In combination, a logic circuit having an output terminal and including a logic tree comprising dynamic MOS logic circuits and a reset circuit operative to charge circuit nodes of the logic tree and to reset the logic tree, and a latch having an input terminal connected to the output terminal of the logic circuit, the latch responsive to a clock signal for periodically latching the output of the logic circuit, the reset circuit comprising a timing circuit connected to the output terminal of the logic circuit and to the input terminal of the latch and responsive to the clock signal to Control the resetting of the logic tree on a clocked basis;

the clock signal having a leading edge and the reset circuit comprising a delay circuit connected to the output terminal of the logic circuit and the timing circuit comprising a logic gate connected to the delay circuit to inhibit operation of the reset circuit until the occurrence of the leading edge of the clock signal.

4. The combination in accordance with claim 3 wherein the delay circuit is adapted to delay the resetting of the logic tree by a predetermined period of time after the occurrence of the leading edge of the clock pulse sufficient to allow the output of the logic circuit to be latched in the latch.

5. The combination in accordance with claim 4 wherein the delay circuit comprises an even number of inverters and the logic gate comprises a NAND gate.