Method and apparatus for erasing an array of electrically erasable programmable read only memory cells

• US 5,488,586 A
• Filed: 10/24/1994
• Issued: 01/30/1996
• Est. Priority Date: 10/24/1994
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Madurawe, Raminda, Schmidt, Dominik
• Primary Examiner(s): YOO, DO H
• Application Number:
  US08/328,303
• Time in Patent Office: 463 Days
• Field of Search: 365/185, 365/218, 365/900
• US Class Current: 365/185.06
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3477 Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing

Abstract

An apparatus and method of erasing memory cells while preventing overerasure of the memory cells is disclosed. By applying a large voltage across the floating gate of the memory cells, charge is removed from the floating gate. Once sufficient charge is removed from the floating gates of the memory cells to render them erased, a stop transistor halts the erasure process, thus preventing the overerasure of memory cells.

Claims

1. An apparatus for erasing memory cells while preventing overerasure of the cells comprising:

a memory cell having a gate, a drain, a source, and a floating gate from which charge must be removed by placing a potential thereacross to erase said memory cell;

an erase node for applying said potential across said floating gate;

a stop transistor having a gate directly coupled to said drain of said memory cell, a source, and a drain directly coupled to said erase node, said stop transistor preventing overerasure of said memory cell when a threshold voltage is reached on said gate of said stop transistor; and

a resistive element having a first terminal coupled to said drain of said stop transistor and a second terminal.

2. The apparatus of claim 1 wherein when the source of said memory cell is coupled to a first voltage, the source of said stop transistor is coupled to a second voltage, the gate of said memory cell is coupled to ground potential, and said second terminal of said resistive element is directly coupled to a third voltage, said third voltage causing removal of said charge from said floating gate of said cell through said erase node, removal of said charge causes a voltage to be induced at said drain of said memory cell such that when sufficient charge is removed from said cell, said induced voltage on said drain causes said stop transistor to conduct and force a voltage drop across said resistive element, said voltage drop causing the erasing of memory cells to stop.

3. The apparatus of claim 2 wherein said voltage drop reduces said potential at said erase node and stops further removal of said charge from said floating gate.

4. The apparatus of claim 1 wherein said memory cell comprises an electronically erasable programmable read only memory.

5. The apparatus of claim 1 wherein said memory cell comprises a flash erasable programmable read only memory.

6. The apparatus of claim 1 wherein said erase node comprises a tunnel diode.

7. The apparatus of claim 2 wherein a threshold erase voltage of said memory cell is altered through control of said first voltage, said second voltage and said third voltage.

8. An apparatus for erasing memory cells while preventing overerasure comprising:

memory cells, each having a gate, a drain, a source, and a floating gate from which charge must be removed by placing a potential thereacross to erase said cell, said cells connected in parallel columns and parallel rows which are orthogonal to said columns;

an erase node associated with each memory cell for applying said potential across the floating gate of said memory cell;

source lines, each coupled to the source of each cell in a column;

drain lines, each coupled to the drain of each cell in a column;

gate lines, each coupled to the gate of each cell in a row;

erase lines, each directly coupled to said erase node of each cell in a column;

stop transistors, each associated with one column and having a gate directly coupled to the drain line of said column, a source, and a drain coupled to the erase line associated with said column; and

resistive elements, each associated with one stop transistor and having a first terminal coupled to the drain of said stop transistor and a second terminal.

9. The apparatus of claim 8 wherein when said source line in a selected column is coupled to a first voltage, the source of said associated stop transistor is coupled to a second voltage, said gate lines are coupled to ground potential, and the second terminal of said associated resistive element coupled to said stop transistor in said selected column is directly coupled to a third voltage, said third voltage causing removal of said charge from the floating gates of said memory cells coupled to said selected column through said erase nodes, removal of said charge causes a voltage to be induced on said drain line of said selected column such that when sufficient charge is removed from any one of said cells in said selected column, said induced voltage of said drain line causes said stop transistor to conduct and force a voltage drop across said associated resistive element, said voltage drop causing the erasing of memory cells to stop.

10. The apparatus of claim 9 wherein said voltage drop reduces said potential at said erase line and stops further removal of said charge from the floating gates of cells coupled to said selected column.

11. The apparatus of claim 8 wherein said memory cells comprise electronically erasable programmable read only memory cells.

12. The apparatus of claim 8 wherein said memory cells comprise flash erasable programmable read only memory cells.

13. The apparatus of claim 8 wherein said erase node comprises a tunnel diode.

14. The apparatus of claim 9 wherein a threshold erase voltage of said memory cell is altered through control of said first voltage, said second voltage and said third voltage.

15. A method for erasing a memory cell in a memory device while preventing overerasure, the memory device comprising the memory cell having a gate, a drain, a source, a floating gate from which charge must be removed by placing a potential thereacross to erase the cell, an erase node for applying the potential across the floating gate, a stop transistor having a gate directly coupled to the drain of the memory cell, a source and a drain directly coupled to the erase node, and a resistive element having a first terminal directly coupled to the drain of the stop transistor and a second terminal, the method comprising the steps of:

applying a first voltage to the source of the memory cell;

applying a second voltage to the source of the stop transistor;

applying ground potential to the gate of the memory cell;

applying a third voltage to the second terminal of the resistive element, said third voltage causing a voltage to be induced at the drain of the memory cell;

activating the stop transistor with said induced voltage; and

forcing a voltage drop across the resistive element, said voltage drop causing erasing of the memory cell to stop.

16. The method of claim 15 wherein the memory cell comprises an electronically erasable programmable read only memory cell.

17. The method of claim 15 wherein the memory cell comprises flash erasable programmable read only memory cell.

18. The method of claim 15 wherein the erase node comprises a tunnel diode.

19. The method of claim 15 further including the step of altering a threshold erase voltage of said memory cell through control of said first voltage, said second voltage and said third voltage.