Method of die burn-in

• US 5,489,538 A
• Filed: 01/09/1995
• Issued: 02/06/1996
• Est. Priority Date: 08/21/1992
• Status: Expired due to Term

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Dell'Oca, Conrad, Rostoker, Michael D.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): TSAI, H JEY
• Application Number:
  US08/370,565
• Time in Patent Office: 393 Days
• Field of Search: 148/DIG. 162, 437/51, 437/226
• US Class Current: 438/15
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: Y10S 148/162 Testing steps

Abstract

The present invention provides for a burn-in test which is conducted on the wafer level, before the dies are separated into individual chips and packaged. In a preferred embodiment of the invention, a series of chips are each connected to an external current, ground, and/or alternate signal source(s) for burn-in. Generally, the method herein for a burn-in of a semiconductor die comprises the step of: (a) providing an electrical connection between a die on a semiconductor wafer and an external current source; (b) heating the semiconductor wafer; and (c) applying a common signal across the electrical connection to burn in the die. A preferred method herein provides a semiconductor wafer including a multiplicity of dies and wafer level test points, at least one layer of conductive lines overlying the semiconductor wafer, a means for connecting an individual conductive line to a test point on the wafer; and a means for connecting the conductive lines to an external signal source for exercising the dies.

Claims

1. Method of burning-in and harvesting a plurality of functional dice from a semiconductor wafer, comprising the steps of:

providing a plurality of sets of bond pads on a semiconductor wafer characterized by a plurality of semiconductor dice, each of the plurality of sets of bond pads associated with corresponding ones of the dice;

depositing an insulating layer on the wafer;

depositing a plurality of conductive lines on the insulating layer for connecting together selected ones of the plurality of sets of bond pads;

connecting an external source of power and test signals to the plurality, of conductive lines, thereby

applying the power and test signals contemporaneously to the selected ones of the plurality of sets of bond pads;

identifying defective ones of the plurality of semiconductor dice;

removing the plurality of conductive lines and insulating layer from the wafer; and

separating the semiconductor wafer into individual dice for packaging into integrated circuits.

2. The method of claim 1, wherein the step of depositing an insulating layer comprises the steps of depositing a plurality of insulating layers.

3. The method of claim 2, wherein the steps of depositing a plurality of insulating layers includes the steps of depositing different ones of the plurality of conductive lines between the plurality of insulating layers so as to make multilevel connections to different ones of the selected ones of the plurality of sets of bond pads.

4. The method of claim 1, wherein the step of removing is by etching the wafer.

5. The method of claim 1, wherein the step of removing is by polish grinding the wafer.