Method of making a 3-dimensional circuit assembly having electrical contacts that extend through the IC layer

• US 5,489,554 A
• Filed: 02/04/1994
• Issued: 02/06/1996
• Est. Priority Date: 07/21/1992
• Status: Expired due to Term

• Current Assignee: Tally Loch Investments LLC (Intellectual Ventures LLC)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: Gates, James L.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): DUTTON, BRIAN KEITH
• Application Number:
  US08/192,207
• Time in Patent Office: 732 Days
• Field of Search: 257/777, 257/774, 437/187, 437/974, 437/209, 437/208, 437/203, 437/86, 437/195, 148/DIG. 12, 148/DIG. 135
• US Class Current: 438/59
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A 3-dimensional circuit assembly includes a lower substrate, a first integrated circuit (IC) layer that is adhered to and electrically insulated from the substrate, electrical contacts for the IC layer, and separate electrical contacts for the substrate that extend through and are insulated from the IC layer. The IC layer is surmounted by an insulating layer through which the electrical contacts also extend, and across which interconnections between different contacts may be made. The IC layer and substrate are held together by an adhesion layer, with the adhesion, IC and insulating layers all being thin enough to assume the coefficient of thermal expansion for the underlying substrate, which is much thicker. The substrate may itself have a second IC layer to which contacts are made, or it may be implemented as the photodetector of a focal plane array. Two standard wafers are used to form the package, with the substrate for the upper wafer removed either before or after bonding to the lower wafer. Additional IC layers may be added by adding additional wafers in a similar fashion.

Claims

1. A method of fabricating a three-dimensional (3-D) circuit assembly, comprising:

providing a first substrate with a first set of at least one electrical contact pad thereon,

adhering a first IC layer to said first substrate and electrically insulating said first IC layer and said first substrate from each other with an adherent material, said first IC layer provided with a layer of insulative material on its opposite side from said adherent material,

establishing a first set of at least one electrical contact to said first IC layer,

forming a first set of at least one opening through said layer of insulative material, said first IC layer and said adherent material to said first set of at least one electrical contact pad on said first substrate

forming a second set of at least one opening through said layer of insulative material and through said first IC layer, said first set of at least one electrical contact extending through said second set of at least one opening,

establishing a second set of at least one electrical contact through said first set of openings to said first set of at least one electrical contact pad on said first substrate.

2. The method of claim 1, wherein said layer of insulative material is initially provided on a second substrate and said second substrate is removed from said layer of insulative material prior to forming said first and second sets of at least one opening.

3. The method of claim 1, wherein said second substrate is removed by etching and said layer of insulative material is used as an etch stop.

4. The method of claim 1, wherein at least some of said first and second sets of at least one electrical contact are extended over said layer of insulative material whereby at least some of said first set of at least one electrical contact is in electrical contact with at least some of said second set of at least one electrical contact.

5. The method of claim 1, further comprising the step of lining said first and second sets of at least one opening with an electrically insulative material before said first and second sets of at least one electrical contact are extended through their respective openings.

6. The method of claim 1, further comprising the steps of forming one additional IC layer over said layer of insulative material, extending said first and second sets of at least one opening and at least one electrical contact through said additional IC layer, forming an additional respective set of at least one opening to said additional IC layer through said insulative layer, and establishing an additional respective set of at least one electrical contact through said additional set of openings to said additional IC layer.

7. The method of claim 1, wherein said adherent material comprises an adhesive and said first IC layer and said first substrate are adhered together by sandwiching said adhesive between them and curing the adhesive.

8. The method of claim 1, wherein said adherent material comprises a layer of thermally fusible material on each of said first IC layer and said first substrate, and said first IC layer and said first substrate are adhered together by sandwiching said layers of thermally fusible material between said first IC layer and said first substrate and thermally fusing said layers of thermally fusible material together.

9. The method of claim 1, wherein said adherent material is a layer whose thermal movements are controlled by said first substrate.

10. The method of claim 1, wherein a second IC layer is provided in said first substrate facing said first IC layer, and said second set of at least one electrical contact is established with said second IC layer.

11. The method of claim 1, wherein said first substrate comprises a photodetector and is provided with an array of pixel contact pads facing said first IC layer, and said second set of at least one electrical contact is established by forming discrete electrically conductive members through said first set of at least one opening to establish electrical contact with respective pixel contact pads.