System for interfacing wafer sort prober apparatus and packaged IC handler apparatus to a common test computer

• US 5,489,852 A
• Filed: 11/06/1992
• Issued: 02/06/1996
• Est. Priority Date: 11/06/1992
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Gomez, Carlos A.
• Primary Examiner(s): Nguyen, Vinh P.
• Application Number:
  US07/973,089
• Time in Patent Office: 1,187 Days
• Field of Search: 324/158 P, 324/158 F, 324/72.5, 324/760, 324/754, 324/755, 324/765, 324/158.1, 439/482, 439/824, 437/8
• US Class Current: 324/756.07
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence

Abstract

A system for interfacing wafer sort prober apparatus and packaged IC handler apparatus to a common test computer is provided that includes a single motherboard and at least one daughter board. The motherboard includes a probe card interface area having a plurality of contactors that mate with symmetrical connectors provided on a probe card. The probe card includes a series of contact probes adapted to make electrical connection to a semiconductor wafer. The motherboard also includes a hole in its center to allow visual inspection and alignment of the wafer when it is positioned beneath the motherboard. A test head interface area is also provided on the motherboard and includes a plurality of contactors that mate with symmetrical contactors provided on a test head assembly of the test computer. The motherboard further includes a daughter board interface area having a plurality of contactors that mate with symmetrical contactors provided on each daughter board. A connector is provided on each daughter board that mates with an IC contactor unit. As a result, a common interface board can be used during both wafer sort testing and packaged IC testing. Cost is thereby reduced since entirely separate boards are not required. The motherboard incorporates interconnecting lines and support interface circuitry common to both wafer sort and packaged IC testing. In addition, by using a packaged IC standard unit (that is, an IC that is known to be completely functional), debugging of the motherboard interconnecting lines and support circuity for the wafer sort configuration is simplified. Debugging of the wafer sort configuration is simplified since the daughter board can be attached directly to the motherboard independent of a prober apparatus, and thus mechanical access to the motherboard is not obstructed.

Claims

1. An apparatus for interfacing a wafer sort prober apparatus or a packaged IC handler apparatus to a common test system, wherein said wafer sort prober apparatus includes a probe card for providing electrical connections to a semiconductor wafer, and wherein said packaged IC handler apparatus includes an IC contactor for providing electrical connections to a packaged integrated circuit, and wherein said common test system includes a test head for providing electrical connections between said test system and an external device, said interfacing apparatus comprising:

a mother interface board having first contactors to electrically contact said test head, a plurality of second contactors to electrically contact said probe card, and a plurality of third contactors; and

a daughter board having a plurality of fourth contactors removably connected to said third contactors and a plurality of fifth contactors to electrically contact said IC contactor unit.

2. An interfacing apparatus as recited in claim 1 wherein said mother interface board includes a center-located hole that allows visual access to said semiconductor wafer when positioned beneath said mother interface board.

3. An interfacing apparatus as recited in claim 1 wherein an outer periphery of said daughter board extends beyond said second contactors such that said second contactors are covered when said daughter board is connected to said mother interface board.

4. An interfacing apparatus as recited in claim 1 wherein said third contactors are female receptacles and wherein said fourth contactors are male connecting pins that mate with said female receptacles.

5. An interfacing apparatus as recited in claim 1 wherein said mother interface board includes a printed circuit board having a plurality of contact pads that form said plurality of first contactors and said plurality of second contactors.

6. An interfacing apparatus as recited in claim 1 wherein said mother interface board includes a plurality of electronic components to support an electrical test of semiconductor wafers and of packaged integrated circuits.

7. An interfacing apparatus as recited in claim 5 wherein said first contactors are first side of said printed circuit board and wherein said second contactors are on a second side of said printed circuit board.

8. An interfacing apparatus as recited in claim 7 wherein said third contactors are on said second side of said printed circuit board.

9. An interfacing apparatus as recited in claim 1 wherein said third and fourth contactors provide for attaching said daughter board to said mother interface board independent of said wafer sort prober apparatus.

10. An interfacing apparatus as recited in claim 1 wherein said third and fourth contactors provide for attaching said daughter board to said mother interface board while preserving mechanical access to said mother interface board.

19. An interfacing apparatus as recited in claim 10 wherein said plurality of contactors of said daughter board interface area and said plurality of contactors of said daughter board provide for attaching said daughter board to said mother interface board independent of said wafer sort prober apparatus

11. An apparatus for interfacing a wafer sort prober apparatus or a packaged IC handler apparatus to a common test computer, said wafer sort prober apparatus for providing electrical connections to a semiconductor wafer, said packaged IC handler apparatus for providing electrical connections to a packaged integrated circuit, and said common test system for controlling test operations performed upon said semiconductor wafer and said packaged integrated circuit, said interfacing apparatus comprising:

a mother interface board including a computer system interface area, a prober apparatus interface area, and a daughter board interface area, wherein said computer system interface area includes a plurality of contactors for providing electrical connections to said test computer, and wherein said prober apparatus interface area includes a plurality of contactors for providing electrical connections to said wafer sort prober apparatus, and wherein said daughter board interface area includes a plurality of contactors; and

a daughter board including a plurality of contactors removably mated with said plurality of contactors included with said daughter board interface area of said mother interface board, and including a connector portion to provide electrical connections to said packaged IC handler apparatus.

12. An interfacing apparatus as recited in claim 11 wherein said mother interface board includes a center-located hole that allows visual access to said semiconductor wafer when positioned beneath said mother interface board.

13. An interfacing apparatus as recited in claim 11 wherein an outer periphery of said daughter board extends beyond said prober apparatus interface area such that said prober apparatus interface area is covered when said daughter board is connected to said mother interface board.

14. An interfacing apparatus as recited in claim 11 wherein said plurality of contactors of said daughter board interface area are female receptacles and wherein said plurality of contactors of said daughter board are male connecting pins that mate with said female receptacles.

15. An interfacing apparatus as recited in claim 11 wherein said mother interface board includes a printed circuit board having a plurality of contact pads that form said plurality of contactors of said computer system interface area and said plurality of contactors of said prober apparatus interface area.

16. An interfacing apparatus as recited in claim 15 wherein said plurality of contactors of said computer system interface area are on a first side of said printed circuit board and wherein said plurality of contactors of said prober apparatus interface area are on a second side of said printed circuit board.

17. An interfacing apparatus as recited in claim 16 wherein said plurality of contactors of said daughter board interface area are on said second side of said printed circuit board.

18. An interfacing apparatus as recited in claim 11 wherein said mother interface board includes a plurality of electronic components to support an electrical test of semiconductor wafers and of packaged integrated circuits.

20. An interfacing apparatus as recited in claim 11 wherein said plurality of female receptacles and said plurality of male pins provide for attaching said daughter board to said mother interface board while preserving mechanical access to said mother interface board.

21. An apparatus for interfacing a wafer sort prober apparatus or a packaged IC handler apparatus to a common test computer, said wafer sort prober apparatus for providing electrical connections to a semiconductor wafer, said packaged IC handler apparatus for providing electrical connections to a packaged integrated circuit, and said common test computer for controlling test operations performed upon said semiconductor wafer and said packaged integrated circuit, said interfacing system comprising:

a mother interface board including a computer system interface area, a prober apparatus interface area, and a daughter board interface area, wherein said computer system interface area includes a plurality of contact pads for providing electrical connections to said test computer, wherein said prober apparatus interface area includes a plurality of contact pads for providing electrical connections to said wafer sort prober apparatus, wherein said daughter board interface area includes a plurality of female receptacles, and wherein said mother interface board includes an open hole positioned at a center portion of said mother interface board; and

a daughter board including a plurality of male pins removably mated with said plurality of female receptacles included with said daughter board interface area of said mother interface board, and including a connector portion that mates with said packaged IC handler apparatus.

22. An apparatus for interfacing a packaged IC handler apparatus to a test head of a test system, said interfacing system comprising:

a mother interface board having a plurality of first contactors to electrically contact said test head, a plurality of second contactors, and interface circuitry coupled between said first and second contactors;

an IC contactor attached to said IC handler apparatus and having a plurality of third contactors; and

a daughter board having a plurality of fourth contactors and a plurality of fifth contactors, said fourth contactors removably contacting said second contactors and said fifth contactors contacting said third contactors.

23. An interfacing apparatus as in claim 22, wherein said second contactors are female receptacles and said fourth contactors are male pins removably mated with said female receptacles.

24. An apparatus for interfacing a probe card and a packaged IC contactor unit to a common test system at different times, said common test system having a test head with a plurality of first contact pins, said apparatus comprising:

a mother interface board having;

a plurality of first contact pads to contact said first contact pins and thereby electrically couple said mother interface board to said test head;

a plurality of second contact pads;

a plurality of first female receptacles; and

an interior edge defining an open hole positioned at the center thereof; and

an integrated circuit test unit removably coupled to said mother interface board, said integrated circuit test unit being one of a probe card and a packaged IC test unit, said probe card including a plurality of second contact pins, and said packaged IC test unit including;

a daughter board having a plurality of second female receptacles and a plurality of first male pins; and

an IC contactor having a plurality of second male pins removably mated with said second female receptacles to electrically couple and mechanically attach said IC contactor to said daughter board;

wherein said second contact pads are contacted by said second contact pins when a wafer probe card is being interfaced, and wherein said first male pins are removably mated with said first female receptacles when a packaged IC test unit is being interfaced.

25. An interfacing apparatus as in claim 24 wherein said IC contactor is an IC contactor for dual in-line packages.

26. An interfacing apparatus as in claim 24 wherein said IC contactor is an IC contactor for plastic leaded chip carrier packages.

27. A common interface board for interfacing a probe card or a packaged IC contactor to a common test system, wherein said common test system includes a test computer and a test head with a plurality of first contactors that provide electrical coupling to said test computer, and wherein said probe card has a plurality of second contactors that provide electrical coupling to said common interface board, said common interface board comprising:

a test head interface area on a first side of said common interface board, said test head interface area having a plurality of third contactors to contact said first contactors on said test head;

a probe card interface area on a second side of said common interface board, said probe card interface area having a plurality of fourth contactors to contact said second contactors on said probe card;

a daughter board interface area on said second side of said common interface board, said daughter board interface area having a plurality of fifth contactors;

a plurality of electronic components coupling said third contactors to said fourth and said fifth contactors, wherein said electronic components are interconnected to form interface circuitry specific to a particular integrated circuit under test, the integrated circuit under test being one of die on a semiconductor wafer and a packaged chip; and

an open hole that allows visual access to the semiconductor wafer when a wafer is positioned beneath said common interface board.

28. A common interface board as in claim 27 wherein said first contactors are contact pins and said third contactors are contact pads.

29. A common interface board as in claim 27 wherein said second contactors are contact pins and said fourth contactors are contact pads.

30. A common interface board as in claim 27 combined with a daughter board, said daughter board having a plurality of sixth contactors removably connected to said fifth contactors, and having a plurality of seventh contactors for electrically contacting said packaged IC contactor.

31. A method of using a common test system to test a device under test selected from a variety of integrated circuit devices, including integrated circuit dies and packaged integrated circuits, comprising:

electrically coupling first terminals of interface circuitry on a mother interface board to the test system;

selecting a contactor for the device under test, the contactor being a probe card when the device under test is an integrated circuit die, and the contactor being a packaged IC contactor when the device under test is a packaged integrated circuit;

electrically coupling second terminals of the interface circuitry on the mother interface board to the probe card when the device under test is an integrated circuit die on a wafer;

electrically coupling the second terminals of the interface circuitry on the mother interface board to a daughter board when the device under test is a packaged integrated circuit; and

electrically coupling the daughter board to the packaged IC contactor when the device under test is a packaged integrated circuit.

32. A method as in claim 31 wherein said step of coupling the second terminals of the interface circuitry on the mother interface board to the daughter board is performed with male pins and female receptacles.