Display data driving integrated circuit

• US 5,489,867 A
• Filed: 06/21/1994
• Issued: 02/06/1996
• Est. Priority Date: 06/21/1993
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tamanoi, Yutaka
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US08/262,875
• Time in Patent Office: 595 Days
• Field of Search: 327/149, 327/158, 327/250, 327/251, 327/269, 327/270, 326/93, 326/96, 345/94, 345/98, 345/99, 345/100, 347/237, 347/238, 347/247
• US Class Current: 327/269
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/025 Reduction of instantaneous peaks of current
• CPC Class Codes: G09G 2330/06 Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: H03G 3/00 Gain control in amplifiers or frequency changers

Abstract

In a display data driving IC for driving a matrix display unit, switching current in a plurality of channel driving buffer circuits is suppressed, and when a multi-tone display unit is driven, the tone display quality is improved. The present invention is characterized by comprising a plurality of channel driving buffer circuits to which the individual bit signals of parallel display data are supplied and which, receiving an operation control signal, amplify the individual bit signals or perform voltage level conversion and output the resulting signals, a plurality of control signal supply lines for supplying the operation control signal to each of a plurality of groups into which the driving buffer circuits are divided, a single operation control signal input terminal to which an operation control signal for controlling the operation of the buffer circuits is supplied, and an operation control signal distribution circuit for distributing the operation control signal input to the plurality of control signal supply lines with a specific timing relationship.

Claims

1. A display data driving integrated circuit comprising:

a plurality of channel driving buffer circuits to which individual bit signals of parallel display data are supplied and which, upon receiving an operation control signal, amplify the individual bit signals or perform voltage level conversion and output the resulting signals;

a plurality of control signal supply lines for supplying said operation control signal to each of a plurality of groups into which said plurality of channel driving buffer circuits are divided;

operation control signal input terminal to which said operation control signal for controlling the operation of said buffer circuits is supplied;

an operation control signal input line connected to said operation control signal input terminal; and

a phase mode control circuit for changing a timing of said supplying of said operation control signal to those of said buffer circuits which are in one group selected from said groups of said buffer circuits to change phase modes of output signals of said buffer circuits of said selected group.

2. A display data driving integrated circuit according to claim 1, wherein said phase mode control circuit comprises:

a delay circuit for delaying said operation control signal supplied from said operation control signal input line and supplying the delayed signal to at least one of said plurality of control signal supply lines;

a switching circuit formed so as to select either a connecting path between said operation control signal input line and said delay circuit or a connecting path between said operation control signal input line and at least one of said plurality of control signal supply lines; and

a switch control signal input terminal to which a switch control signal for controlling said switching circuit is supplied.

3. A display data driving integrated circuit according to claim 1, wherein said phase mode control circuit comprises:

a delay circuit for delaying said operation control signal supplied from said operation control signal input line and supplying the delayed signal to at least one of said plurality of control signal supply lines; and

a wire formed so as to select either a connecting path between said operation control signal input line and said delay circuit or a connecting path between said delay circuit and at least one of said plurality of control signal supply lines.

4. A display data driving integrated circuit according to claim 1, wherein said phase mode control circuit changes said timing of said supplying of said operation control signal to said buffer circuits of said selected group to change said phase modes of said output signals of said buffer circuits of said selected group.

5. A display data driving integrated circuit according to claim 4, wherein said phase mode control circuit comprises:

a delay circuit for receiving and delaying said operation control signal; and

a switch circuit for allowing said operation control signal on said operation control signal input line or an output signal of said delay circuit, to be supplied to said buffer circuits of said selected group in accordance with a switch control signal.

6. A display data driving integrated circuit according to claim 5, wherein said phase mode control circuit further includes a switch control signal input terminal to which said switch control signal is supplied.

7. A display data driving integrated circuit according to claim 1, wherein said phase mode control circuit comprises:

a plurality of delay circuits having different delay times, for receiving and delaying said operation control signal; and

a switch circuit for allowing output signals of said delay circuits to be supplied to said buffer circuits of said selected group, in a corresponding relationship or another relationship between said delay circuits and said buffer circuits of said selected group, in accordance with a switch control signal.

8. A display data driving integrated circuit according to claim 7, wherein said phase mode control circuit further includes a switch control signal input terminal to which said switch control signal is supplied.