Adaptive feedforward linearizer for RF power amplifiers

• US 5,489,875 A
• Filed: 09/21/1994
• Issued: 02/06/1996
• Est. Priority Date: 09/21/1994
• Status: Expired due to Term

• Current Assignee: Andrew LLC (CommScope Holding Company, Inc.)
• Original Assignee: Simon Fraser University
• Inventors: Cavers, James K.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US08/309,478
• Time in Patent Office: 503 Days
• Field of Search: 330/149, 330/151
• US Class Current: 330/151
• CPC Class Codes: H03F 1/3229 using a loop for error extraction and another loop for error subtraction
• CPC Class Codes: H03F 2201/3212 Using a control circuit to adjust amplitude and phase of a signal in a signal path

Abstract

A feed forward amplifier circuit for amplifying an input signal to produce an amplified replica thereof. A first splitter splits the input signal into first and second signal cancellation branches. The first signal cancellation branch contains an amplifier and a first "delay, gain and phase adjuster" (DGPA) connected in series between a-first output of the first splitter and the amplifier; and, a second splitter connected in series with the amplifier'"'"'s output for splitting the amplified output signal into first and second distortion cancellation branches. The second signal cancellation branch contains a first delay line connected in series between a second output of the first splitter and a first input of a first combiner. The second splitter has a first output coupled to a second input of the first combiner. The first distortion cancellation branch contains a second delay line connected in series between a second output of the second splitter and a first input of a second combiner. The second distortion cancellation branch contains a third splitter connected in series between the first combiner and a second DGPA, and an auxiliary amplifier connected in series between the second DGPA and a second input of the second combiner. A first controller is connected between an output of the third splitter and the first DGPA to adapt the first DGPA to changes in signals at the third splitter'"'"'s output and to changes in signals output by the first DGPA. A second controller is connected between an output of a fourth splitter and the second DGPA to adapt the second DGPA to changes in signals at, the fourth splitter'"'"'s output and to changes in signals output by the second DGPA. The fourth splitter is connected to receive the output of the second combiner and provides the amplified replica at its output.

Claims

1. A feed forward amplifier circuit for amplifying an input signal to produce an amplified replica thereof, said circuit comprising:

a first splitter (S1) for splitting said input signal into first and second signal cancellation branches;

said first signal cancellation branch comprising an amplifier (A1) for producing an amplified output signal (20), first delay, gain and phase adjusting means (DGPA1) connected in series between a first output (10) of said first splitter (S1) and said amplifier (A1), and a second splitter (S2) connected in series with said amplifier output (20) for splitting said amplified output signal (20) into first and second distortion cancellation branches;

said second signal cancellation branch comprising a first delay line (DL1) connected in series between a second output (30) of said first splitter (S1) and a first input (40) of a first combiner (C1);

said second splitter (S2) having a first output (25) coupled to a second input of said first combiner (C1);

said first distortion cancellation branch comprising a second delay line (DL2) connected in series between a second output (65) of said second splitter (S2) and a first input (70) of a second combiner (C2);

said second distortion cancellation branch comprising a third splitter (S4) connected in series between said first combiner (C1) and a second delay, gain and phase adjusting means (DGPA2), an auxiliary amplifier (A2) connected in series between said second delay, gain and phase adjusting means (DGPA2) and a second input (60) of said second combiner (C2);

a first controller (CT3) connected between an output (100) of said third splitter (S4) and said first delay, gain and phase adjuster (DGPA1), said first controller (CT3) for adapting said first delay, gain and phase adjuster (DGPA1) to changes in signals at said output (100) and to changes in signals (R, RD) output by said first delay, gain and phase adjuster (DGPA1);

a second controller (CT4) connected between an output (85) of a fourth splitter (S6) and said second delay, gain and phase adjuster (DGPA2), said second controller (CT4) for adapting said second delay, gain and phase adjuster (DGPA2) to changes in signals at said output (85) and to changes in signals (R, RD) output by said second delay, gain and phase adjuster (DGPA2);

said fourth splitter (S6) connected to receive the output (75) of said second combiner (C2); and

, said fourth splitter (S6) providing said amplified replica at its output (80).

2. A feed forward amplifier circuit as defined in claim 1, wherein said first and second delay, gain and phase adjusters (DGPA1, DGPA2) each comprise:

a fifth splitter (S7) for splitting a selected input signal (I) between main and delayed signal branches;

said main signal branch comprising a sixth splitter (S8) for splitting said main branch signal to provide said output (R) and an input (155) of a first complex gain adjuster (CGA3);

said delayed signal branch comprising a third delay line (DL3) for delaying said input signal (I) connected in series between said fifth splitter (S7) and a seventh splitter (S9) for splitting said delayed signal to provide said output (RD) and an input (140) of a second complex gain adjuster (CGA4); and

,

a third combiner (C3) having first and second inputs (145,

     160) connected to receive signals output by said first and second complex gain adjusters (CGA3, CGA4) respectively.

3. A feed forward amplifier circuit as defined in claim 2, further comprising:

means (S10, C5) for subtractively coupling said delayed signal into said main signal branch for input to said sixth splitter (S8); and

,

means (S11, C4) for additively coupling said input signal (I) into said delayed signal branch for input to said seventh splitter (S9).

4. A feed forward amplifier circuit as defined in claim 1, wherein said first and second controllers (CT3, CT4) each comprise:

first and second bandpass correlators (BPC1, BPC2) for receiving said signals at said respective outputs (100,

     85) and said (R) and (RD) output signals, and for outputting signals (GA, GB, GAD, GBD) to said first and second delay, gain and phase adjusters (DGPA1, DGPA2) respectively;

wherein;

while outputting said signals (GA, GB) said first bandpass correlator (BPC1) drives to zero correlation between said signals at said respective outputs (100,

     85) and said (R) output signal; and

,

while outputting said signals (GAD, GBD) said second bandpass correlator (BPC2) drives to zero correlation between said signals at said respective outputs (100,

     85) and said (RD) output signal.

5. A feed forward amplifier circuit as defined in claim 1, 2 or 3, wherein said first and second controllers (CT3, CT4) each comprise:

first and second bandpass correlators (BPC3, BPC4) for receiving said signals at said respective outputs (100,

     85) and said (R) and (RD) output signals, and for outputting signals (GA, GB, GAD, GBD) to said first and second delay, gain and phase adjusters (DGPA1, DGPA2) respectively; and

,

means (LO1;

M1, BPF1;

M2, BPF2;

M3, BPF3) for selecting desired frequency components of said respective received signals and for reducing said respective received signals to a common intermediate frequency prior to delivery of said received signals to said respective first and second bandpass correlators (BPC3, BPC4).

6. A feed forward amplifier circuit as defined in claim 1, 2 or 3, wherein said first and second controllers (CT3, CT4) each comprise:

a digital signal processor (DSP1) for bandpass correlating said signals at said respective outputs (100,

     85) with said (R) and (RD) output signals, and for outputting signals (GA, GB, GAD, GBD) to said first and second delay, gain and phase adjusters (DGPA1, DGPA2) respectively;

means (LO1;

M1, BPF1;

M2, BPF2;

M3, BPF3) for selecting desired frequency components of said respective received signals and for reducing said respective received signals to a common intermediate frequency prior to delivery of said received signals to said digital signal processor (DSP1); and

,

means (LO2;

M4, BPF4;

M5, BPF5;

M6, BPF6) for further reducing said respective received signals to a low frequency prior to delivery of said received signals to said digital signal processor (DSP1).

7. A feed forward amplifier circuit for amplifying an input signal to produce an amplified replica thereof, said circuit comprising:

a first splitter (S1) for splitting said input signal into first and second signal cancellation branches;

said first signal cancellation branch comprising an amplifier (A1) for producing an amplified output signal (20), a first adjuster (DGPA1) for adjusting complex gain attributes of signals input to said amplifier, said first adjuster connected in series between a first output (10) of said first splitter (S1) and said amplifier (A1), and a second splitter (S2) connected in series with said amplifier output (20) for splitting said amplified output signal (20) into first and second distortion cancellation branches;

said second signal cancellation branch comprising a first delay line (DL1) connected in series between a second output (30) of said first splitter (S1) and a first input (40) of a first combiner (C1);

said second splitter (S2) having a first output (25) coupled to a second input of said first combiner (C1);

said first distortion cancellation branch comprising a second delay line (DL2) connected in series between a second output (65) of said second splitter (S2) and a first input (70) of a second combiner (C2);

said second distortion cancellation branch comprising a third splitter (S4) connected in series between said first combiner (C1) and a second adjuster (DGPA2) for adjusting complex gain attributes of signals input to an auxiliary amplifier (A2), said auxiliary amplifier (A2) connected in series between said second adjuster (DGPA2) and a second input (60) of said second combiner (C2);

a first controller (CT3) connected between an output (100) of said third splitter (S4) and said first adjuster (DGPA1), said first controller comprising a power detector (PD1) for converting signals at said output (100) to a representation of power in said signals at said output (100) and for inputting said representation to a digital signal processor (DSP2) for adjusting output signals (GA, GB, GAD, GBD) of said first controller (CT3) to minimize said representation; and

,

a second controller (CT4) connected between an output (85) of a fourth splitter (S6) and said second adjuster (DGPA2), said second controller (CT4) comprising a second power detector for converting signals at said output (85) to a second representation of power in said signals at said output (85) and for inputting said second representation to a second digital signal processor for adjusting output signals (GA, GB, GAD, GBD) of said second controller (CT4) to minimize said second representation;

said fourth splitter (S6) connected to receive the output (75) of said second combiner (C2); and

,

said fourth splitter (S6) providing said amplified replica at its output (80).

8. A feed forward amplifier circuit as defined in claim 7, wherein said digital signal processor (DSP2) maintains internal variables (GASUM, GBSUM, GADIFF, GBDIFF) from which said output signals (GA, GB, GAD, GBD) are determined, and said adjustment comprises:

(a) applying small initial perturbations to said internal variables (GASUM, GBSUM, GADIFF, GBDIFF) and corresponding perturbations to said output signals (GA, GB, GAD, GBD) to yield a resultant value of said representation;

(b) measuring said resultant value of said representation;

(c) deriving components (GRADGASUM, GRADGBSUM, GRADGADIFF, GRADGBDIFF) of an estimated gradient of said representation with respect to said internal variables (GASUM, GBSUM, GADIFF, GBDIFF);

(d) deriving adjusted values of said internal variables (GASUM, GBSUM, GADIFF, GBDIFF) by subtracting a portion of said components (GRADGASUM, GRADGBSUM, GRADGADIFF, GRADGBDIFF) from said internal variables (GASUM, GBSUM, GADIFF, GBDIFF); and

,

(e) applying said output signals (GA, GB, GAD, GBD) determined from said adjusted values.

9. A feed forward amplifier circuit as defined in claim 7 or 8, wherein said first and second controllers (CT3, CT4) respectively further comprise:

means (LO3;

M7, BPF7) for sequentially selectively reducing desired frequency components of said respective received signals to a range of common intermediate frequencies prior to delivery of said received signals to said digital signal processor (DSP2) to yield a series of said representations corresponding to each of said intermediate frequencies;

wherein said first and second controllers (CT3, CT4) respectively sum said representations to yield a resultant value of said representation.

10. A feed forward amplifier circuit for amplifying an input signal to produce an amplified replica thereof, said circuit comprising:

a first splitter (S1) for splitting said input signal into first and second signal cancellation branches;

said first signal cancellation branch comprising an amplifier (A1) for producing an amplified output signal (20), a first adjuster (DGPA1) for adjusting complex gain attributes of signals input to said amplifier, said first adjuster connected in series between a first output (10) of said first splitter (S1) and said amplifier (A1), and a second splitter (S2) connected in series with said amplifier output (20) for splitting said amplified output signal (20) into first and second distortion cancellation branches;

said second signal cancellation branch comprising a first delay line (DL1) connected in series between a second output (30) of said first splitter (S1) and a first input (40) of a first combiner (C1);

said second splitter (S2) having a first output (25) coupled to a second input of said first combiner (C1);

said first distortion cancellation branch comprising a second delay line (DL2) connected in series between a second output (65) of said second splitter (S2) and a first input (70) of a second combiner (C2);

said second distortion cancellation branch comprising a third splitter (S4) connected in series between said first combiner (C1) and a second adjuster (DGPA2) for adjusting complex gain attributes of signals input to an auxiliary amplifier (A2), said auxiliary amplifier (A2) connected in series between said second adjuster (DGPA2) and a second input (60) of said second combiner (C2);

a first controller (CT3) connected between an output (100) of said third splitter (S4) and said first adjuster (DGPA1), said first controller (CT3) for receiving signals at said output (100) and signals (R) output by said first adjuster (DGPA1), said first controller comprising a first bandpass correlator (BPC3) for outputting signals (GA, GB) to said first adjuster (DGPA1) and means (LO1;

M1, BPF1;

M2, BPF2) for selecting desired frequency components of said received signal (100) and for reducing said received signal to an intermediate frequency prior to delivery of said received signal to said first bandpass correlator (BPC3); and

,

a second controller (CT4) connected between an output (85) of a fourth splitter (S6) and said second adjuster (DGPA2), said second controller (CT4) for receiving signals at said output (85) and signals (R) output by said second adjuster (DGPA2), said second controller comprising a second bandpass correlator (BPC4) for outputting signals (GA, GB) to said second adjuster (DGPA2) and means (LO1;

M1, BPF1;

M2, BPF2) for selecting desired frequency components of said received signal (85) and for reducing said received signal to an intermediate frequency prior to delivery of said received signal to said second bandpass correlator (BPC4);

said fourth splitter (S6) connected to receive the output (75) of said second combiner (C2); and

,

said fourth splitter (S6) providing said amplified replica at its output (80).

11. A feed forward amplifier circuit as defined in claim 10, wherein said first and second controllers (CT3, CT4) each comprise:

a digital signal processor (DSP1) for bandpass correlating said signals at said respective outputs (100,

     85) with said (R) output signal, and for outputting said signals (GA, GB) to said first and second adjusters (DGPA1, DGPA2) respectively;

means (LO1;

M1, BPF1;

M2, BPF2) for selecting desired frequency components of said respective received signals and for reducing said respective received signals to a common intermediate frequency prior to delivery of said received signals to said digital signal processor (DSP1); and

,

means (LO2;

M4, BPF4;

M5, BPF5) for further reducing said respective received signals to a low frequency prior to delivery of said received signals to said digital signal processor (DSP1).

12. A feed forward amplifier circuit for amplifying an input signal to produce an amplified replica thereof, said circuit comprising:

a first splitter (S1) for splitting said input signal into first and second signal cancellation branches;

said first signal cancellation branch comprising an amplifier (A1) for producing an amplified output signal (20), a first adjuster (DGPA1) for adjusting complex gain attributes of signals input to said amplifier, said first adjuster connected in series between a first output (10) of said first splitter (S1) and said amplifier (A1), and a second splitter (S2) connected in series with said amplifier output (20) for splitting said amplified output signal (20) into first and second distortion cancellation branches;

said second signal cancellation branch comprising a first delay line (DL1) connected in series between a second output (30) of said first splitter (S1) and a first input (40) of a first combiner (C1);

said second splitter (S2) having a first output (25) coupled to a second input of said first combiner (C1);

said first distortion cancellation branch comprising a second delay line (DL2) connected in series between a second output (65) of said second splitter (S2) and a first input (70) of a second combiner (C2);

said second distortion cancellation branch comprising a third splitter (S4) connected in series between said first combiner (C1) and a second adjuster (DGPA2) for adjusting complex gain attributes of signals input to an auxiliary amplifier (A2), said auxiliary amplifier (A2) connected in series between said second adjuster (DGPA2) and a second input (60) of said second combiner (C2);

a first controller (CT3) connected between an output (100) of said third splitter (S4) and said first adjuster (DGPA1), said first controller comprising a power detector (PD1) for converting signals at said output (100) to a representation of power in said signals at said output (100) and for inputting said representation to a digital signal processor (DSP2) for continuously estimating the power gradient of said representation and for outputting signals (GA, GB) to said first adjuster (DGPA1) while adjusting said output signals (GA, GB) to minimize said representation; and

,

a second controller (CT4) connected between an output (85) of a fourth splitter (S6) and said second adjuster (DGPA2), said second controller (CT4) comprising a second power detector for converting signals at said output (85) to a second representation of power in said signals at said output (85) and for inputting said second representation to a second digital signal processor for continuously estimating the power gradient of said second representation and for outputting signals (GA, GB) to said second adjuster (DGPA2) while adjusting said output signals (GA, GB) to minimize said second representation;

said fourth splitter (S6) connected to receive the output (75) of said second combiner (C2); and

,

said fourth splitter (S6) providing said amplified replica at its output (80).

13. A feed forward amplifier circuit as defined in claim 12, further comprising, in each of said first and second controllers (CT3, CT4), means (LO3;

M7, BPF7) for sequentially selectively reducing desired frequency components of said respective signals (100,

     85) to a range of common intermediate frequencies prior to delivery of said signals (100,

     85) to said respective power detectors to yield a series of said representations corresponding to each of said intermediate frequencies; and

wherein said first and second controllers (CT3, CT4) respectively sum said representations to yield said resultant value of said representation.

14. A method of linearizing an amplifier by deriving a distortion signal representative of IM distortion in signals output by said amplifier and applying said distortion signal to cancel distortion in said amplifier output signal to yield a substantially distortion-free replica of said amplifier output signal, wherein:

(a) said distortion signal derivation step further comprises;

(i) approximating said distortion signal by subtractively combining said amplifier output signal with an input signal to be amplified;

(ii) reducing said approximated distortion signal to an intermediate frequency;

(iii) selecting desired frequency components of said approximated intermediate frequency distortion signal;

(iv) bandpass correlating said desired frequency components with said input signal;

(v) applying said bandpass correlation to adaptively adjust complex gain attributes of signals input to said amplifier;

(vi) subtractively combining said complex gain adjusted amplifier output signal with said input signal to yield said distortion signal;

(b) said distortion cancellation step further comprises;

(i) approximating said distortion-free replica by subtractively combining said amplifier output signal with said distortion signal;

(ii) reducing said approximated replica to an intermediate frequency;

(iii) selecting desired frequency components of said approximated intermediate frequency replica;

(iv) bandpass correlating said desired frequency components of said approximated replica with said distortion signal;

(v) applying said bandpass correlation of said approximated replica and distortion signal to adaptively adjust complex gain attributes of said distortion signal; and

,

(vi) subtractively combining said amplifier output signal with said complex gain adjusted distortion signal to yield said replica.

15. A method of linearizing an amplifier by deriving a distortion signal representative of IM distortion in signals output by said amplifier and applying said distortion signal to cancel distortion in said amplifier output signal to yield a substantially distortion-free replica of said amplifier output signal, wherein:

(a) said distortion signal derivation step further comprises;

(i) approximating said distortion signal by subtractively combining said amplifier output signal with an input signal to be amplified;

(ii) deriving a signal representative of power in said approximated distortion signal;

(iii) perturbing complex gain attributes of signals input to said amplifier;

(iv) deriving a corresponding perturbed signal representative of power in said approximated distortion signal;

(v) iteratively repeating steps (a) (i)-(a) (iv) while, for each iteration, deriving further signals representative of power in said approximated distortion signal;

(vi) estimating the power gradient of said further signals;

(vii) adaptively adjusting, in a direction opposite to said power gradient estimate, said complex gain attributes of signals input to said amplifier;

(viii) subtractively combining said complex gain adaptively adjusted amplifier output signal with said input signal to yield said distortion signal;

(b) said distortion cancellation step further comprises;

(i) approximating said distortion-free replica by subtractively combining said amplifier output signal with said distortion signal;

(ii) deriving a signal representative of power in said approximated distortion-free replica;

(iii) perturbing complex gain attributes of said distortion signals;

(iv) deriving a corresponding perturbed signal representative of power in said approximated distortion-free replica;

(v) iteratively repeating steps (b)(i)-(b)(iv) while, for each iteration, deriving further signals representative of power in said distortion-free replica;

(vi) estimating the power gradient of said further signals derived in step (b)(v);

(vii) adaptively adjusting, in a direction opposite to said step (b)(vi) estimate, said complex gain attributes of said distortion signal; and

,

(viii) subtractively combining said amplifier output signal with said step complex gain adaptively adjusted distortion signal to yield said replica.