Current-controlled quadrature oscillator based on differential g.sub.m /C cells

• US 5,489,878 A
• Filed: 11/23/1994
• Issued: 02/06/1996
• Est. Priority Date: 11/23/1994
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Gilbert, Barrie
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US08/344,361
• Time in Patent Office: 440 Days
• Field of Search: 331/57, 331/108 R, 331/111, 331/114, 331/115, 331/135, 331/136, 331/177 R
• US Class Current: 331/57
• CPC Class Codes: H03B 5/20 with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H03K 3/0231 Astable circuits H03K3/0315 takes precedence
• CPC Class Codes: H03L 5/00 Automatic control of voltage, current, or power

Abstract

An oscillator including two gm/C stages is disclosed. Each gm/C stage includes a differential pair of transistors, a capacitor, and a tunable current source. Alternatively, multi-tanh n-tuplets can be used in place of the differential pairs in the gm/C stages to increase the linearity of the gm/C stage. The gm/C stages include a pair of input terminals, a pair of output terminals, and a pair of common-mode terminals. The two gm/C stages are interconnected in a feedback loop to form a quadrature oscillator. A common-mode biasing circuit is coupled a supply voltage and each pair of common-mode terminals for biasing the respective gm/C stage. The common-mode biasing circuits can include: current mirrors, diode pairs, and even resistors. An optional start-up circuit can be coupled to each gm/C stage to ensure start-up of the associated gm/C stage. The start-up circuit includes a pair of cross-coupled transistors in order to form a negative resistance so as to compensate for the impedance of the subsequent gm/C stage.

Claims

1. An oscillator comprising:

a first gm/C integrator stage having a first pair of input terminals, a first pair of output terminals, and a first pair of common-mode terminals;

a first common-mode biasing means coupled between a supply voltage and the first pair of common-mode terminals;

a second gm/C integrator stage having a second pair of input terminals, a second pair of output terminals, and a second pair of common-mode terminals;

a second common-mode biasing means coupled between a supply voltage and the second pair of common-mode terminals; and

wherein the first pair of output terminals is coupled to the second pair of input terminals and the second pair of output terminals is cross-coupled to the first pair of input terminals such that a signal appearing on the first pair of input terminals is 180 degrees out of phase with a concomitant signal appearing on the second pair of input terminals whereby the oscillator oscillates.

2. An oscillator according to claim 1 further including:

a first start-up means coupled to the first pair of output terminals; and

a second start-up means coupled to the second pair of output terminals.

3. An oscillator according to claim 2 wherein the first start-up means includes means for producing a negative resistance, wherein the absolute value of the negative resistance is equal to or greater than the absolute value of an input resistance of the second gm/C integrator stage.

4. An oscillator according to claim 2 wherein the first start-up means includes:

a pair of cross-coupled transistors; and

a current source coupled to the pair of cross-coupled transistors for providing a bias current thereto.

5. An oscillator according to claim 2 further including means coupled between the supply voltage and the first pair of output terminals for limiting the amplitude of a signal appearing across the first pair of output terminals.

6. An oscillator according to claim 5 wherein the means coupled between the supply voltage and the first pair of output terminals for limiting the amplitude of a signal appearing across the first pair of output terminals includes a first pair of amplitude limiting diodes, wherein each one of the first pair of amplitude limiting diodes is coupled between the supply voltage and a respective one of the first pair of output terminals.

7. An oscillator according to claim 2 wherein the first common-mode biasing means includes a first pair of biasing resistors, each one of the first pair of biasing resistors coupled between the supply voltage and a respective one of the first pair of output terminals.

8. An oscillator according to claim 2 wherein the first common-mode biasing means includes a first pair of biasing diodes connected in series and a second pair of biasing diodes connected in series, each pair of biasing diodes coupled between the supply voltage and a respective one of the first pair of output terminals.

9. An oscillator according to claim 1 wherein the first common-mode biasing means includes:

a first current mirror including a first diode-connected transistor having a base and being coupled between the supply voltage and a first one of the first pair of output terminals and including a first mirror transistor having a base and being coupled between the supply voltage and a second one of the first pair of output terminals, the base of the first diode-connected transistor being coupled to the base of the first mirror transistor; and

a second current mirror including a second diode-connected transistor having a base and being coupled between the supply voltage and the second one of the first pair of output terminals and including a second mirror transistor having a base and being coupled between the supply voltage and the first one of the first pair of output terminals, the base of the second diode-connected transistor being coupled to the base of the second mirror transistor.

10. An oscillator according to claim I wherein the first gm/C integrator stage includes a first multi-tanh n-tuplet.

11. An oscillator comprising:

a first gm/C integrator stage having a first pair of input terminals, a first pair of output terminals, and a first pair of common-mode terminals;

a first pair of common-mode transistors coupled between a supply voltage and the first pair of common-mode terminals, each one of the first pair of common mode transistors being coupled between the supply voltage and a respective one of the first pair of common-mode terminals, each one of the first pair of common mode transistors having a control terminal;

a first common-mode biasing transistor having a control terminal coupled to a second gm/C integrator stage and a load terminal coupled to the control terminals of the first pair of common-mode transistors;

a first start-up means coupled to the first pair of output terminals;

the second gm/C integrator stage having a second pair of input terminals, a second pair of output terminals, and a second pair of common-mode terminals;

a second pair of common-mode transistors coupled between the supply voltage and the second pair of common-mode terminals, each one of the second pair of common mode transistors being coupled between the supply voltage and a respective one of the second pair of common-mode terminals, each one of the second pair of common mode transistors having a control terminal;

a second common-mode biasing transistor having a control terminal coupled to the first gm/C integrator stage and a load terminal coupled to the control terminals of the second pair of common-mode transistors; and

a second start-up means coupled to the second pair of output terminals;

wherein the first pair of output terminals is coupled to the second pair of input terminals and the second pair of output terminals is cross-coupled to the first pair of input terminals such that a signal appearing on the first pair of input terminals is 180 degrees out of phase with a concomitant signal appearing on the second pair of input terminals whereby the oscillator oscillates.

12. An oscillator according to claim 11 wherein the first pair of common-mode transistors include a first pair of lateral PNP transistors.

13. An oscillator according to claim 11 wherein the first pair of common-mode transistors include a first pair of complementary bipolar PNP transistors.

14. An oscillator according to claim 11 wherein the first common-mode biasing transistor includes a vertical PNP transistor.

15. An oscillator according to claim 11 wherein the first start-up means includes:

a first pair of cross-coupled transistors coupled to the first pair of output terminals; and

a first biasing current source coupled to the first pair of cross-coupled transistors.

16. An oscillator according to claim 15 further including means coupled between the supply voltage and the first pair of output terminals for limiting the amplitude of a signal appearing across the first pair of output terminals.

17. An oscillator according to claim 16 wherein the means coupled between the supply voltage and the first pair of output terminals for limiting the amplitude of a signal appearing across the first pair of output terminals includes a first pair of amplitude limiting diodes, wherein each one of the first pair of amplitude limiting diodes is coupled between the supply voltage and a respective one of the first pair of output terminals.

18. An oscillator comprising:

a first gm/C integrator stage having a first pair of input terminals, a first pair of output terminals, and a first pair of common-mode terminals;

a first common-mode biasing means coupled between a supply voltage and the first pair of common-mode terminals;

a first pair of cross-coupled transistors coupled to the first pair of output terminals;

a first biasing current source coupled to the first pair of cross-coupled transistors;

a second gm/C integrator stage having a second pair of input terminals, a second pair of output terminals, and a second pair of common-mode terminals;

a second common-mode biasing means coupled between a supply voltage and the second pair of common-mode terminals; and

a second pair of cross-coupled transistors coupled to the second pair of output terminals; and

a second biasing current source coupled to the second pair of cross-coupled transistors;

wherein the first pair of output terminals is coupled to the second pair of input terminals and the second pair of output terminals is cross-coupled to the first pair of input terminals such that a signal appearing on the first pair of input terminals is 180 degrees out of phase with a concomitant signal appearing on the second pair of input terminals whereby the oscillator oscillates.

19. An oscillator according to claim 18 further including means coupled between the supply voltage and the first pair of output terminals for limiting the amplitude of a signal appearing across the first pair of output terminals.

20. An oscillator according to claim 19 further including means coupled between the supply voltage and the second pair of output terminals for limiting the amplitude of a signal appearing across the second pair of output terminals.

21. An oscillator according to claim 19 wherein the means coupled between the supply voltage and the first pair of output terminals for limiting the amplitude of a signal appearing across the first pair of output terminals includes a first pair of amplitude limiting diodes, wherein each one of the first pair of amplitude limiting diodes is coupled between the supply voltage and a respective one of the first pair of output terminals.

22. An oscillator according to claim 18 wherein the first common-mode biasing means coupled between a supply voltage and the first pair of common-mode terminals includes:

a first pair of common-mode transistors coupled between a supply voltage and the first pair of common-mode terminals, each one of the first pair of common mode transistors being coupled between the supply voltage and a respective one of the first pair of common-mode terminals, each one of the first pair of common mode transistors having a control terminal; and

a first common-mode biasing transistor having a control terminal coupled to the second gm/C integrator stage and a load terminal coupled to the control terminals of the first pair of common-mode transistors.

23. An oscillator according to claim 18 wherein the first common-mode biasing means coupled between a supply voltage and the first pair of common-mode terminals includes:

a first current mirror including a first diode-connected transistor having a base and being coupled between the supply voltage and a first one of the first pair of output terminals and including a first mirror transistor having a base and being coupled between the supply voltage and a second one of the first pair of output terminals, the base of the first diode-connected transistor being coupled to the base of the first mirror transistor; and

a second current mirror including a second diode-connected transistor having a base and being coupled between the supply voltage and the second one of the first pair of output terminals and including a second mirror transistor having a base and being coupled between the supply voltage and the first one of the first pair of output terminals, the base of the second diode-connected transistor being coupled to the base of the second mirror transistor.

24. An oscillator according to claim 23 wherein the first diode-connected transistor is a PNP transistor having a base, an emitter, and a collector, the emitter of the first diode-connected transistor being coupled to the supply voltage and the collector of the first diode-connected transistor being coupled to one of the first pair of output terminals;

wherein the first mirror transistor is a PNP transistor having a base, an emitter, and a collector, the emitter of the first mirror transistor being coupled to the supply voltage and the collector of the first mirror transistor being coupled to the other one of the first pair of output terminals; and

wherein the base of the first diode-connected transistor is coupled to the base of the first mirror transistor.

25. An oscillator according to claim 24 wherein the ratio of the first diode-connected transistor emitter area to the first mirror transistor emitter area is equal to 1:

1+δ

.

26. An oscillator according to claim 18 wherein the first gm/C integrator stage includes:

a first differential pair of transistors, each transistor having a base, a collector, and an emitter, wherein the collectors of the differential pair comprise the first pair of output terminals;

a first capacitor coupled across the first pair of output terminals; and

a first controllable current source coupled to the emitters of the differential pair of transistors, wherein the frequency of oscillation is responsive to the current in the first controllable current source.

27. An oscillator according to claim 26 wherein the first capacitor includes a pair of capacitors connected in parallel.

28. An oscillator comprising:

a first gm/C integrator stage having a first pair of input terminals, a first pair of output terminals, and a first pair of common-mode terminals;

a first common-mode biasing circuit coupled between a supply voltage and the first pair of common-mode terminals;

a second gm/C integrator stage having a second pair of input terminals, a second pair of output terminals, and a second pair of common-mode terminals;

a second common-mode biasing circuit coupled between a supply voltage and the second pair of common-mode terminals; and

wherein the first pair of output terminals is coupled to the second pair of input terminals and the second pair of output terminals is cross-coupled to the first pair of input terminals such that a signal appearing on the first pair of input terminals is 180 degrees out of phase with a concomitant signal appearing on the second pair of input terminals whereby the oscillator oscillates.

29. An oscillator according to claim 28 wherein the first common mode biasing circuit comprises:

a first biasing transistor being coupled between the supply voltage and a first one of the first pair of common mode terminals, the first biasing transistor having a control terminal coupled to a second one of the first pair of common mode terminals;

a first diode coupled between the supply voltage and the control terminal of the first biasing transistor;

a second biasing transistor being coupled between the supply voltage and the second one of the first pair of common mode terminals, the second biasing transistor having a control terminal coupled to the first one of the first pair of common mode terminals; and

a second diode coupled between the supply voltage and the control terminal of the second biasing transistor.

30. An oscillator according to claim 28 further comprising means for tuning the oscillator.

31. An oscillator according to claim 30 wherein the means for tuning the oscillator includes:

a tuning transistor having a control terminal, a bias terminal, and a supply terminal, the control terminal for receiving a frequency control signal, the bias terminal being coupled to the first and second gm/C stages for providing a bias current thereto, and the supply terminal being coupled to the supply voltage.

32. An oscillator according to claim 31 wherein the means for tuning the oscillator further includes:

a capacitor coupled between the control terminal and the bias terminal of the tuning transistor; and

a biasing transistor coupled to the tuning transistor.

33. An oscillator according to claim 31 wherein the first and second gm/C stages include first and second tunable current sources, respectively.

34. An oscillator according to claim 33 wherein the bias terminal of the tuning transistor is coupled to the first and second tunable current sources to modulate the current supplied by the tunable current sources, wherein the frequency of oscillation modulates responsive thereto.

35. A method of tuning an oscillation frequency of an oscillation signal generated by an oscillator having a pair of gm/C integrator stages, each gm/C stage having a tunable current source coupled thereto for sourcing current from the associated gm/C stage, the method comprising:

cross-coupling the pair of gm/C stages to form a closed loop;

applying a control signal to the oscillator;

altering the currents through the gm/C stages responsive to the control signal; and

altering the transconductance (grn) of the integrator stages responsive to the alteration in the currents wherein the oscillation frequency is tuned.

36. A method of tuning an oscillation frequency of an oscillator according to claim 35 including starting up the oscillator.

37. A method of tuning an oscillation frequency of an oscillator according to claim 36 wherein the step of starting up the oscillator includes locating a pole for each gm/C stage in the right hand plane.

38. A method of tuning an oscillation frequency of an oscillator according to claim 37 wherein the step of locating a pole for each gm/C stage in the right hand plane includes providing a negative impedance to each gm/C stage.

39. A method of tuning an oscillation frequency of an oscillator according to claim 35 wherein the step of altering the currents through the gm/C stages responsive to the control signal includes supplying a bias current to the tunable current sources responsive to the control signal.

40. A method of tuning an oscillation frequency of an oscillator according to claim 35 including providing a common-mode bias current to each of the gm/C stages.

41. A method of tuning an oscillation frequency of an oscillator according to claim 35 including limiting the amplitude of the oscillation.