Bypass switching and messaging mechanism for providing intermix data transfer for a fiber optic switch

• US 5,490,007 A
• Filed: 10/31/1994
• Issued: 02/06/1996
• Est. Priority Date: 10/31/1994
• Status: Expired due to Fees

• Current Assignee: Mcdata Corporation (Broadcom, Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Bennett, Dwayne R., Wu, Wayne, Yeung, Clifford S.
• Primary Examiner(s): Boudreau, Leo H.
• Assistant Examiner(s): NEGASH, KINFE MICHAEL
• Application Number:
  US08/332,185
• Time in Patent Office: 463 Days
• Field of Search: 359/109, 359/118, 359/119, 359/128, 359/137, 359/139, 359/152, 370/53, 370/60.1
• US Class Current: 398/52
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3027 Output queuing
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/357 Fibre channel switches

Abstract

A system and method for inserting intermix frames into a continuous stream of class 1 frames. A bypass bus, in conjunction with a first-in-first-out (FIFO) buffer, are provided within a fiber optic switch element, to route intermix data frame through the switch that is concurrently transmitting class 1 data. A channel module, which is disposed between a switch module and a plurality of fiber optic channels, comprises a port intelligence system and a memory interface system. The port intelligence system is responsible for transmitting and receiving data from the fiber optic channels in accordance with a predetermined protocol, preferably Fibre Channel. The memory interface system comprises a receive memory unit, a transmit memory unit and memory control logic. When an intermix frame is to be passed through the switch, the intermix frame is passed to a FIFO concurrently while class 1 data transfer occurs via the bypass bus. After the intermix frame has been completely written into the FIFO, the memory control logic waits to detect a tag indicative of a break in the class 1 data transfer. The control logic will then switch the MUX and cause the FIFO to commence writing the intermix frame to the port intelligence system for transfer to a predetermined fiber optic channel.

Claims

1. A system for providing the capability to accommodate intermix data transfer in a fiber optic switch, the switch is connected to a fiber optic channel, the system comprising:

a port intelligence system configured to transmit and receive data from the fiber optic channel according to a first protocol;

a memory interface system connected to the port intelligence system, the memory interface system comprising

a buffer configured to receive intermix data, the buffer having an input and an output;

a bypass bus connected to the input of the buffer;

a MUX connected to the output of the buffer and the bypass bus; and

a transmit control logic unit connected to the buffer and the MUX, the transmit control logic unit controls both the buffer and the MUX to transfer intermix data.

2. The system of claim 1, wherein the first protocol is Fibre Channel.

3. The system of claim 2, wherein the transmit control logic sends a bypass control signal to the MUX, the bypass control signal instructs the MUX to switch between the buffer output and the bypass bus.

4. The system of claim 3, wherein the transmit control logic sends a control signal to the buffer, the control signal instructs the buffer to read data from the buffer input and write data to the MUX.

5. The system of claim 4, wherein the buffer is a 16 k×

9 FIFO.

6. A method for injecting intermix data into a continuous stream of class 1 data, the continuous stream of class 1 data being transferred through a fiber optic switch, the fiber optic switch having an input and an output, the method comprising the steps of:

(1) transferring the continuous stream of class 1 data from the input to the output via a bypass bus;

(2) writing an intermix frame to a memory unit;

(3) determining whether subsequent class 1 data will follow the intermix frame;

(4) writing the subsequent class 1 data to the memory unit if class 1 follows the intermix frame;

(5) determining when an idle appears in the continuous stream of class 1 data;

(6) writing the intermix frame from the memory unit to the output when the idle appears in the continuous stream of class 1 data; and

(7) writing the subsequent class 1 data from the memory unit to the output.