Detecting false-locking and coherent digital demodulation using the same

• US 5,490,176 A
• Filed: 10/20/1992
• Issued: 02/06/1996
• Est. Priority Date: 10/21/1991
• Status: Expired due to Fees

• Current Assignee: Societe Anonyme DBA
• Original Assignee: Societe Anonyme DBA
• Inventors: Peltier, Jacques
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US07/963,559
• Time in Patent Office: 1,204 Days
• Field of Search: 375/324-328, 375/344, 375/345, 329/304, 329/306-310, 348/528, 348/536
• US Class Current: 375/325
• CPC Class Codes: H04L 2027/0057 quadrature phase
• CPC Class Codes: H04L 27/2273 associated with quadrature demodulation, e.g. Costas loop

Abstract

In a method of detecting false-locking the trains of clock signals corresponding to the two phase offset initially modulated trains of signals, the phase offset between said trains of clock signals is monitored, and false-locking is detected when the phase offset changes signal. Also, a method of demodulation implements this method of detecting false-locking. Also, a device for implementing the method of detecting false-locking contains a flip-flop in series with a monostable.

Claims

1. A method of detecting false-locking of a reference signal onto a digitally quadrature modulated signal with multiple levels and phase offset and demodulated by coherent digital demodulation, said digitally quadrature modulated signal containing bit stream signals, said method comprising the steps of:

mixing said digitally quadrature modulated signal with a first reference signal and with a second reference signal which is in phase quadrature with the first reference signal, in order to obtain baseband analog signals corresponding to the bit stream signals,

recovering, from said baseband analog signals, trains of clock signals which correspond to said bit stream signals;

monitoring the phase offset between said trains of clock signals;

detecting false-locking when the phase offset changes sign; and

correcting the first and second reference signals, when false-locking is detected, to lock the first and second reference signals in frequency and phase with the digitally quadrature modulated signal.

2. A method of coherent digital demodulation of a signal which contains bit stream signals and which is initially digitally modulated with multiple levels and phase offset, said method comprising the steps of:

mixing said signal to be demodulated with a first reference signal and with a second reference signal which is in phase quadrature with the first reference signal, in order to obtain baseband analog signals corresponding to the bit stream signals,

regenerating bit stream signals of the baseband analog signals thus obtained;

recovering, from said baseband analog signals, trains of clock signals which correspond to said bit stream signals;

monitoring the phase offset between said trains of clock signals;

detecting false-locking when the phase offset changes sign; and

correcting the first and second reference signals, when false-locking is detected, to lock the first and second reference signals in frequency and phase with the signal to be demodulated.

3. The method of coherent digital demodulation according to claim 2, further comprising the step of detecting modulo π

the phase of the first reference signal when the direction of the phase offset between said trains of clock signals take a predetermined value.

4. The method of coherent digital demodulation according to claim 3, further comprising the step of:

correcting the first reference signal only when one of said trains of clock signals obtained by mixing the signal to be demodulated with the first reference signal is in advance relative to another of said trains of clock signals obtained by mixing the second reference signal with the signal to be demodulated, in such a manner that a phase to which the first reference signal is locked is established modulo π

.

5. A device for detecting false-locking of a reference signal onto a digitally quadrature modulated signal with multiple levels in phase offset and demodulated by coherent digital demodulation, said device comprising:

a direct demodulation circuit for mixing the digitally quadrature modulated signal, said direct demodulation circuit comprising;

a receiver oscillator providing a first reference signal;

a first mixer for mixing the digitally quadrature modulated signal with the first reference signal and for providing a first baseband analog signal; and

a second mixer for mixing the digitally quadrature modulated signal with a second reference signal which is in phase quadrature with the first reference signal and for providing a second baseband analog signal;

first and second clock recovery circuits for receiving the first and second baseband analog signals, respectively, and for recovering first and second trains of clock signals, respectively;

a detector adapted to detect changes in a direction of a phase offset between the first and second trains of clock signals; and

a ramp generator coupled to said detector, which commands said receiver oscillator in order to correct said first and second reference signals to lock said first and second reference signals in frequency and phase with the digitally quadrature modulated signal, when said detector detects changes in the direction of the phase offset between the first and second trains of clock signals.

6. A device for detecting false-locking of a reference signal onto a digitally quadrature modulated signal with multiple levels in phase offset and demodulated by coherent digital demodulation, said device comprising:

a direct demodulation circuit for mixing the digitally quadrature modulated signal, said direct demodulation circuit comprising;

a receiver oscillator providing a first reference signal;

a first mixer for mixing the digitally quadrature modulated signal with the first reference signal and for providing a first baseband analog signal; and

a second mixer for mixing the digitally quadrature modulated signal with a second reference signal which is in phase quadrature with the first reference signal and for providing a second baseband analog signal;

first and second clock recovery circuits for receiving the first and second baseband analog signals, respectively, and for recovering first and second trains of clock signals, respectively;

a detector adapted to detect changes in a direction of a phase offset between the first and second trains of clock signals, wherein said detector comprises;

a flip-flop receiving the second train of clock signals on its clock input and receiving the first train of clock signals on another input, to produce an output signal; and

a monostable circuit receiving the output signal of said flip-flop; and

a ramp generator coupled to said detector, which commands said receiver oscillator in order to correct said first and second reference signals to lock said first and second reference signals in frequency and phase with the digitally quadrature modulated signal, when said detector detects changes in the direction of the phase-offset between the first and second trains of clock signals.

7. The device according to claim 6, wherein said flip-flop is a D-type flip-flop.

8. A device for performing coherent digital demodulation of a signal to be demodulated which contains bit stream signals and which has been modulated with multiple levels and phase offset, said device comprising:

a direct demodulation circuit for mixing the signal to be demodulated, said direct demodulation circuit comprising;

a receiver oscillator providing a first reference signal;

a first mixer for mixing the signal to be demodulated with the first reference signal and for providing a first baseband analog signal; and

a second mixer for mixing the signal to be demodulated with a second reference signal which is in phase quadrature with the first reference signal and for providing a second baseband analog signal, said first and second baseband analog signals corresponding to the bit stream signals;

first and second clock recovery circuits for receiving the first and second baseband analog signals, respectively, and for recovering first and second trains of clock signals, respectively;

first and second regenerating samplers for receiving the first and second baseband analog signals, respectively, and the first and second trains of clock signals, respectively, and for regenerating bit streams of the first and second baseband analog signals, respectively;

a false-locking detector device comprising a flip-flop receiving the second train of clock signals on its clock input and receiving the first train of clock signals on another input, to produce an output signal; and

a monostable circuit receiving the output signal of said flip-flop;

a carrier recovery circuit for receiving the regenerated bit streams of the first and second baseband analog signals and for generating an output signal which controls a phase of the receiver oscillator; and

a voltage ramp circuit for generating an output signal which controls a frequency of the receiver oscillator based on an output signal from said monostable circuit and the output signal from the carrier recovery circuit.