Phase-locked loop circuit having ring oscillator

• US 5,490,182 A
• Filed: 05/24/1994
• Issued: 02/06/1996
• Est. Priority Date: 05/25/1993
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Arai, Masanobu
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): VO, DON NGUYEN
• Application Number:
  US08/248,254
• Time in Patent Office: 623 Days
• Field of Search: 375/376, 331/1 R, 331/1 A, 331/34, 331/57, 331/187, 327/156, 327/158, 327/159
• US Class Current: 375/376
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator

Abstract

A phase-locked loop circuit has a ring oscillator comprising a plurality of 1st, 2nd, . . . , nth inverter chains composed of series-connected 21, 22, . . . , 2n inverters (n≧2), respectively, an (n+1)th inverter chain composed of an odd number of series-connected inverters, and a plurality of 1st-nth selectors associated with the 1st-nth inverter chains, respectively, for selectively outputting input signals to and output signals from the 1st-nth inverter chains, the 1st-nth inverter chains being combined respectively with the 1st-nth selectors in respective combinations, the combinations and the (n+1)th inverter chain being connected in a ring configuration. A phase comparator compares an input clock signal and an oscillated clock signal from the ring oscillator in phase, and applies an output signal to a control circuit which controls the 1st-nth selectors to synchronize the oscillated clock signal with the input clock signal.

Claims

1. A phase-locked loop circuit comprising:

ring oscillator means comprising a plurality of 1st, 2nd, . . . , nth inverter chains composed of series-connected 2^m, 2², . . . , 2ⁿ inverters (n≧

2), respectively, an (n+1)th inverter chain composed of an odd number of series-connected inverters, and a plurality of 1st-nth selectors associated with said 1st-nth inverter chains, respectively, for selectively outputting either input signals or output signals of respective said 1st-nth inverter chains, said 1st-nth inverter chains being combined respectively with said 1st-nth selectors and with said (n+1)th inverter chain in a ring configuration which outputs an oscillated clock signal;

phase comparator means for comparing an input clock signal and the oscillated clock signal; and

control circuit means responsive to an output signal from said phase comparator means for controlling said 1st-nth selectors to synchronize said oscillated clock signal with said input clock signal.

2. A phase-locked loop circuit according to claim 1, wherein said control circuit means comprises means for controlling said 1st-nth selectors while a changing signal cycling through said ring oscillator means is passing through said (n+1)th inverter chain.

3. A phase-locked loop circuit according to claim 1, wherein said control circuit means comprises an up/down counter for counting up or down pulses of said oscillated clock signal depending on the output signal from said phase comparator means, and controlling said 1st-nth selectors with control bits thereof successively in ascending order.

4. A phase-locked loop circuit according to claim 1, wherein said phase comparator means comprises a D flip-flop having a data input terminal for inputting said input clock signal and a clock input terminal for inputting said oscillated clock signal.

5. A phase-locked loop circuit according to claim 3, wherein said ring oscillator means further comprises an (n+2)th inverter chain having two series-connected inverters, and an (n+1)th selector for selectively outputting either an input signal or an output signal of said (n+2)th inverter chain, and wherein said control circuit comprises means for controlling said (n+1)th selector with a signal that represents a value that is m bits lower than a value represented by a bit of said up/down counter for controlling said first selector such that the output signal of said (n+2)th inverter chain is selected by the (n+1)th selector once while a changing signal is cycling 2^m times through said ring oscillator means.

6. A phase-locked loop circuit according to claim 5, wherein said control circuit means comprises means for controlling said (n+1)th selector with the output signal from said phase comparator means.

7. A phase-locked loop circuit according to claim 1, wherein said phase comparator means comprises means for comparing the input clock signal and a chain oscillated clock signal at the input of said (n+1)th inverter chain.

8. A phase-locked loop circuit according to claim 1, wherein said (n+1)th inverter chain is connected between said 1st inverter chain and said nth inverter chain.

9. A phase-locked loop circuit according to claim 8, wherein the oscillated clock signal is output from a first of said odd number of series connected inverters of said (n+1)th inverter chain.