Voltage multiplier using switched capacitance technique

• US 5,491,623 A
• Filed: 09/23/1994
• Issued: 02/13/1996
• Est. Priority Date: 09/23/1994
• Status: Expired due to Fees

• Current Assignee: Fluke Corporation (Fortive Corp.)
• Original Assignee: Fluke Corporation (Fortive Corp.)
• Inventors: Jansen, Marinus J.
• Primary Examiner(s): Wong, Peter S.
• Assistant Examiner(s): BERHANE, ADOLF D
• Application Number:
  US08/311,470
• Time in Patent Office: 508 Days
• Field of Search: 363/59, 363/60, 320/1, 307/110, 327/535, 327/536
• US Class Current: 363/60
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 7/483 Converters with outputs that each can have more than two voltages levels

Abstract

A voltage multiplier is constructed using a series combination of capacitors and an associated switching circuit which provides for charging each capacitor in the series by sequentially connecting each capacitor to a d.c. input voltage. The number of capacitors in the series combination is selectable by the user. The d.c. input voltage of N volts is converted to an a.c. output voltage of peak-to-peak N+1 times the input voltage developed off a tap in the series combination using the pattern of sequential switching. The choice of tap determines the relative offset voltage of the output waveform desired. The relative charging times of the capacitors are chosen so that the output waveform resembles a sine wave to minimize the production of harmonics.

Claims

1. A voltage multiplier comprising:

(a) a plurality of capacitors disposed in an output ladder network having at least one tap, each capacitor having a sufficient amount of capacitance to substantially maintain a charge voltage over a period of an alternating current output waveform;

(b) a plurality of switches for selectably coupling each of said capacitors to an input voltage for a selected charging time wherein each of said capacitors is charged at least once during said period; and

(c) an output terminal coupled to said tap in said output ladder network to form said alternating current output waveform.

2. A voltage multiplier of claim 1 wherein said alternating current output waveform substantially approximates a sine wave by varying the length of said charging times.

3. A voltage multiplier of claim 1 wherein said input voltage is a d.c. voltage.

4. A voltage multiplier of claim 1 wherein each of said capacitors in said output ladder network is charged sequentially.

5. A voltage multiplier for multiplying a d.c. voltage to obtain an alternating current output waveform, comprising:

(a) a plurality of capacitors disposed in an output ladder network having at least one tap, each capacitor having a sufficient amount of capacitance to substantially maintain a charge voltage over a period of said alternating current output waveform;

(b) a plurality of switches for selectably coupling each of said capacitors to said d.c. voltage for a selected charging time wherein each of said capacitors is charged sequentially over said period; and

(c) an output terminal coupled to said tap in said output ladder network of capacitors to form said alternating current output waveform wherein said alternating current output waveform substantially approximates a sine wave by varying the length of said charging times.