Flexibilitiy for column redundancy in a divided array architecture

• US 5,491,664 A
• Filed: 09/27/1993
• Issued: 02/13/1996
• Est. Priority Date: 09/27/1993
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Phelan, Cathal G.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): MAI, SON LUU
• Application Number:
  US08/127,241
• Time in Patent Office: 869 Days
• Field of Search: 365/200, 365/230.03, 371/10.2, 371/10.3
• US Class Current: 365/200
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme

Abstract

An apparatus and method for implementing flexible redundancy memory block elements in a divided array architecture scheme. The apparatus comprising the plurality of memory sub-arrays. Each of the memory sub-arrays includes a plurality of memory blocks having unique addresses and at least one redundancy memory block having a programmable element. Each of the memory sub-arrays is coupled to a plurality of global wordlines which are not uniquely addressed. The memory sub-arrays, namely the memory and redundancy memory blocks, are coupled to a true global read bus to allow the redundancy memory in one memory sub-array to be shared by another sub-array. The method comprises the steps needed to practice the present invention.

Claims

1. A memory device operating in an architecture scheme having a plurality of memory sub-arrays, said memory device comprising:

a storage element, said storage element being uniquely addressed;

an activating element for activating at least one memory cell within said storage element;

a first selecting element for selecting said storage element and being coupled to said storage element;

a second selecting element for selecting said activating element and being coupled to said activating element;

a bus element for reading information from said at least one memory cell within said storage element, wherein said bus element is coupled to said storage element; and

an alternative storage element for alternatively storing information in the event that said storage element is defective permanently disabling said defective storage element and programming an unique address of said defective storage element for said alternative storage element, said alternative storage element being coupled to said activating and bus elements, wherein said defective storage element and said alternative storage element are located in either the same or separate of said plurality of memory sub-arrays, said alternative storage element including at least one redundancy memory block,

wherein said at least one redundancy memory block includes a programmable element, and wherein said programmable element includes a sense amplifier.

2. A memory device operating in an architecture scheme having a plurality of memory sub-arrays for storing data, a location for storing binary data is obtained from an address signal including a block address and a wordline address, said memory device comprising:

at least one decoder for decoding the address signal and activating a selected memory block and at least one selected wordline;

a plurality of memory blocks for each of said plurality of memory sub-arrays coupled to said at least one decoder, said plurality of memory blocks containing a predetermined number of memory cells for storing data, each of said plurality of memory blocks contained within said plurality of sub-arrays having an unique block address so that only a selected one of said plurality of memory blocks in said plurality of memory sub-arrays is activated by said decoder at any time;

a plurality of wordlines for each of said plurality of memory sub-arrays coupled to said at least one decoder, wherein said plurality of wordlines have global wordline addresses so that at least one of said plurality of wordlines in each of said plurality of memory sub-arrays is activated by said at least one decoder;

a global read bus for reading said data from said plurality of memory cells within said selected memory block, wherein said global read bus is coupled to at least one bitline from said plurality of memory blocks and wherein said global read bus comprises a plurality of read bus lines; and

at least one redundancy memory block coupled to said global read bus, wherein said at least one redundancy memory block includes a programmable element for permanently coupling a bitline from said redundancy memory block to any read bus line in said plurality of read bus lines, wherein said at least one redundancy memory block can replace any of said plurality of memory blocks in any of said plurality of memory sub-arrays.

3. The memory device according to claim 2, wherein the programmable element includes a sense amplifier.

4. An integrated circuit memory device for storing data, said memory device comprising:

a first decoder for decoding an address;

a plurality of memory sub-arrays on said integrated circuit, each of said plurality of memory sub-arrays comprising a plurality of memory blocks containing a plurality of memory cells for storing data, each of said plurality of memory blocks being coupled to said first decoder and having an unique block address so that only one of said plurality of memory blocks in said plurality of memory sub-arrays is selected by said first decoder at any time;

a second decoder for decoding an address signal;

a plurality of wordlines for each of said plurality of memory sub-arrays, said plurality of wordlines being coupled to said second decoder, wherein said plurality of wordlines have global wordline addresses such that at least one of said plurality of wordlines in each of said plurality of memory sub-arrays is selected by said second decoder;

a read bus for reading said data, said read bus being ,coupled to each of said plurality of memory sub-arrays, said read bus having a plurality of read bus lines; and

at least one redundancy memory block coupled to said first decoder and coupled to said read bus, said at least one redundancy memory block comprising a programmable element for permanently coupling an output from said at least one redundancy memory block to any read bus line of said plurality of read bus lines, wherein said at least one redundancy memory block can replace any of said plurality of memory blocks in any of said plurality of memory sub-arrays.

5. A method for providing flexible redundancy memory with a divided array architecture scheme, said method comprising the steps of:

forming a plurality of memory sub-arrays from a single memory array, each of said plurality of memory sub-arrays having a plurality of memory blocks and at least one redundancy memory block;

coupling a first decoder to said plurality of memory blocks and the at least one redundancy memory block;

configuring each of said plurality of memory blocks to be uniquely addressable so that only one of said plurality of memory blocks in said plurality of memory sub-arrays is addressed at any time;

coupling a read bus including at least one read bus line to said plurality of memory blocks in said plurality of memory sub-arrays;

coupling a programmable element to each of said at least one redundancy memory block, wherein said programmable element is permanently coupled to each of said at least one read bus line; and

coupling a plurality of wordlines between a second decoder and the plurality of memory blocks and the at least one redundancy memory within each memory sub-array, wherein said plurality of wordlines are not uniquely addressable.