Fault tolerant digital computer system having two processors which periodically alternate as master and slave

• US 5,491,787 A
• Filed: 08/25/1994
• Issued: 02/13/1996
• Est. Priority Date: 08/25/1994
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Hashemi, Seyed H.
• Primary Examiner(s): Nguyen, Hoa T.
• Assistant Examiner(s): Fisch, Alan M.
• Application Number:
  US08/296,302
• Time in Patent Office: 537 Days
• Field of Search: 395/575, 395/425, 371/68.1, 371/16.1, 371/9.1
• US Class Current: 714/11
• CPC Class Codes: G06F 11/1637 using additional compare functionality in one or some but not all of the redundant processing components
• CPC Class Codes: G06F 11/1641 where the comparison is not performed by the redundant processing components
• CPC Class Codes: G06F 11/1654 where the output of only one of the redundant processing components can drive the attached hardware, e.g. memory or I/O

Abstract

In a multiprocessor system, at least one processor is acting as a master processor and another processor is acting as the slave or shadow processor that checks operation of the first processor. Periodically, a controller switches operating mode of a master or main processor to slave or shadow mode, and at the same time switches operation of a slave or shadow processor to main or master processing mode. The first processor is then used as a slave or shadow processor to check operation of the second processor.

Claims

1. A method of operating a fault tolerant digital computer system of the type which includes first and second processors with each such processor having a) a standalone master operating mode and b) a slave mode for monitoring the other processor, said method comprising the steps of:

running said system in one state for a predetermined time interval where said first processor is in said master mode and said second processor is in said slave mode;

running said system in an opposite state for another predetermined time interval where said second processor is in said master mode and said first processor is in said slave mode; and

,

periodicly switching the operation of said system from said one state to said opposite state, and vice-versa, such that said first and second processors are in said master mode during respective time intervals which are interleaved.