Power-on sequencing apparatus for initializing and testing a system processing unit

• US 5,491,790 A
• Filed: 04/22/1994
• Issued: 02/13/1996
• Est. Priority Date: 10/15/1991
• Status: Expired due to Term

• Current Assignee: Bull HN Information Systems Incorporated (Atos SE)
• Original Assignee: Bull HN Information Systems Incorporated (Atos SE)
• Inventors: Petry, Keith L., Keeley, James W., Nibby, Chester M. Jr., Lemay, Richard A., Hirsch, Thomas S.
• Primary Examiner(s): Kim, Ken S.
• Application Number:
  US08/231,856
• Time in Patent Office: 662 Days
• Field of Search: 395/400, 395/425, 395/575, 395/725, 395/183.12, 395/405, 395/421.07, 371/16.1
• US Class Current: 714/36
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 9/4403 Processor initialisation

Abstract

A processing unit couples to a system bus in common with a peer processor, a main memory, in addition to other units, and includes a microprocessor which tightly couples to a local memory also accessible from such bus. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which is coupled to the microprocessor and the system bus. The EEPROM unit stores in first and second separate regions, both of which occupy the same address space normally allocated for storing the microprocessor'"'"'s boot code, on-board diagnostic (OBD) routines and operating system boot routines, respectively. EEPROM control circuits at power-up, condition the EEPROM unit to address the first region for executing OBD routines to verify that the processing unit is operating properly, including the ability to properly issue commands to units connected to the system bus. Following loading of the peer processor operating system, the EEPROM control circuits, in response to commands from the system bus, enable the microprocessor to address the second region for executing boot routines for loading its operating system.

Claims

1. Power on sequence apparatus for use with a processing unit which couples to a system bus and issues commands to any one of a plurality of units coupled in common with said processing unit for carrying out data processing operations, said processing unit including a microprocessor coupled to a synchronous local bus for issuing said commands to said system bus, said apparatus comprising:

an electrically erasable programmable read only memory (EEPROM) unit including at least first and second groups of addressable locations, each first and second groups including a starting location normally referenced by said microprocessor for executing a boot-up routine sequence when said processing unit is powered on and placed in an initial state,

said first group of locations assigned an address space addressable by said microprocessor when in said initial state, said first group of locations storing routines of on-board diagnostic (OBD) routines for testing said processing unit; and

,

said second group of addressable locations having the same address space addressable by said microprocessor when in said initial state for storing said boot-up routine sequence; and

,

control circuit means coupled to said EEPROM unit and to said system bus, said control circuit means including mode indicator means having a plurality of states, said mode indicator means being switched to a first state in response to a signal from said system bus generated when said processing unit is powered on, said mode indicator mean when in said first state supplying at least one signal for causing said EEPROM unit to allow said microprocessor to address only said first group of locations including said starting location, storing said OBD routines for enabling both testing and initialization of said processing unit and when said mode indicator means is switched from said first state to a second one of said plurality of states upon completing said testing for supplying a signal for causing said EEPROM unit to allow said microprocessor to address only said second group of locations including said starting location of said boot-up sequence without having to change normal microprocessor addressing for said boot-up routine sequence.

2. Power on sequence apparatus for use with a processing unit which couples to a system bus and issues commands to any one of a plurality of units coupled in common with said processing unit for performing data processing operations, said processing unit including a microprocessor coupled to a synchronous local bus for issuing said commands to said system bus, said apparatus comprising:

an electrically erasable programmable read only memory (EEPROM) unit including at least first and second groups of addressable locations, each first and second groups including a starting location normally referenced by said microprocessor for executing a boot-up routine sequence when said processing unit is powered on and placed in an initial state,

said first group of locations assigned an address space addressable by said microprocessor when in said initial state, said first group of locations storing routines of on-board diagnostic (OBD) routines for testing said processing unit; and

,

said second group of addressable locations having the same address space addressable by said microprocessor when in said initial state for storing said boot-up routine sequence; and

,

control circuit means coupled to said EEPROM unit and to said system bus, said control circuit means including programmable array logic (PAL) circuit means coupled to said system bus for receiving control and command signals, said PAL including mode indicator means having a plurality of states, said PAL circuit means switching said mode indicator means to a first state in response to a master clear signal from said system bus generated as part of a system initialization procedure when said processing unit is powered on, said mode indicator mean when in said first state supplying at least one signal for causing said EEPROM unit to allow said microprocessor to address only said first group of locations including said starting location, storing said OBD routines for enabling both initialization and testing of said processing unit to verify that said processing unit is operational and when said mode indicator means is switched from said first state to a second one of said plurality of states upon completing said testing for supplying a signal for causing said EEPROM unit to allow said microprocessor to address only said second group of locations including said starting location of said boot-up sequence without having to change normal microprocessor addressing for said boot-up routine sequence.

3. The processing unit of claim 2 wherein said microprocessor includes internal self-test routines and wherein said PAL circuit includes means for generating a reset signal to said microprocessor causing said microprocessor to execute said internal self-test routines for verifying that said microprocessor is operational.

4. The apparatus of claim 3 wherein said processing unit includes register means for storing indications of error conditions, said microprocessor in response to said OBD routines issuing a first I/O command for setting a predetermined indicator when said OBD routines were successfully completed.

5. The apparatus of claim 4 wherein said microprocessor in response to successful completion of said OBD routines issues a second I/O command to suspend its operation awaiting receipt of commands from said system.

6. The apparatus of claim 5 wherein said plurality of units includes a system processor operating under control of an operating system, said system processor upon completion of said processing unit testing, issuing a sequence of I/O commands for determining the operational status of said processing unit and wherein said processing unit further includes a plurality of system visible registers connected to said system bus, different ones of said visible registers for storing system information pertinent to coordinating operations between said processing unit and said system processor and said plurality of system visible registers including said register means, a first I/O command causing said processing unit to read out the contents of register means for determining if said processing unit is operational.

7. The apparatus of claim 6 wherein said system processor upon determining that said processing unit did not successfully execute said OBD routines, issues a second I/O command containing a predetermined function code and bits in certain states, said PAL circuit means in response to said second I/O command generating a reset signal for causing said microprocessor to repeat execution of said built in self-test routines and said OBD routines.

8. The apparatus of claim 6 wherein said system processor upon determining that said processing unit successfully executed said OBD routines issues a number of I/O commands for verifying that said boot routine sequence is valid by causing a data validation operation to be performed.

9. The apparatus of claim 8 wherein said system processor following said number of I/O commands issues a final I/O command containing said predetermined function code having predetermined bits coded to specify a change in mode.

10. The apparatus of claim 9 wherein said PAL circuit means in response to said final I/O command switches said mode indicator from said first state to said second state causing said microprocessor to address said second group of locations to execute said boot routine stored in said EEPROM unit thereby completing initialization.

11. The apparatus of claim 6 wherein said processing unit further includes an addressable local memory coupled to said local bus in common with said microprocessor and wherein said plurality of system visible registers include a memory module register coupled to said system bus and to said microprocessor, said microprocessor in response to said power on signal issuing an I/O command to said system bus specifying loading of said memory module register with a predetermined value during powering up, said predetermined value defining a base address for said local memory as seen from said system bus which places said base address of said local memory outside an address range supported by said system bus preventing interference from other units connected to said system bus.

12. The apparatus of claim 11 wherein said microprocessor during execution of said OBD routines issues an I/O command to said system bus for loading said memory module register with a different value for enabling said processing unit to execute system bus operations without interference from other like processing units connected to said system bus which include local memories.