Cache system using mask bits to recorder the sequences for transfers of data through cache to system memory

• US 5,491,811 A
• Filed: 04/20/1992
• Issued: 02/13/1996
• Est. Priority Date: 04/20/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Siegel, David W., Arimilli, Ravi K., Dhawan, Sudhir
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Asta, Frank J.
• Application Number:
  US07/871,322
• Time in Patent Office: 1,394 Days
• Field of Search: 395/425, 364/252.3, 364/252.5, 364/947.4, 364/958, 364/958.2, 364/958.3, 364/242.3, 364/242.31, 364/243.41, 364/259.7, 364/964.6
• US Class Current: 711/144
• CPC Class Codes: G06F 12/0859 with reload from main memory

Abstract

Apparatus and method for improving the rate of transfer of data in the context of a system memory operated in conjunction with a cache. In one form, mask bits in a mask bit register are associated to bytes of cache. The mask bits are changed in state when the corresponding byte in the cache is written. The mask bits are used in a reordered operating sequence to selectively write data from system memory into the cache after a write into cache. Data transfer performance is improved significantly in that the selective writing of data from system memory to cache can be completely eliminated when the mask bits indicate that a whole unit of the cache, typically a cache line, has been written during the data transfer into the cache.

Claims

1. Apparatus for controlling a transfer of data involving a data cache and memory of a computer system, comprising:

a bus connecting the computer system memory and the computer system data cache;

means for transferring data into the computer system data cache;

at least one data unit in the computer system data cache, the at least one data unit comprising a plurality of groups of bits;

a plurality of mask bits, wherein each of the plurality of mask bits is associated with one of the plurality of groups of bits;

means for relating a given state of each of the plurality of mask bits bit to changes in the group of bits associated with that mask bit; and

means for transferring data from the computer system memory to the computer system data cache in response to the given states of the plurality of mask bits.

2. The apparatus recited in claim 1, wherein the means for transferring data from the computer system memory to the computer system data cache eliminates a read from the computer system memory when the given state of each of the plurality of mask bits coincides with the given states of each of the other of the plurality of mask bits.

3. The apparatus recited in claim 2, wherein the means for transferring data from the computer system memory to the computer system data cache transfers data from the computer system memory to the computer system data cache selectively by groups of bits.

4. The apparatus recited in claim 4, wherein the at least one data unit comprises a cache line.

5. The apparatus recited in claim 4, wherein each Of the plurality of groups of bits comprises one byte.

6. A method of operating a computer system to perform a data transfer between a data cache of the computer system and a computer system memory, comprising the steps of:

transferring data into the computer system data cache, wherein the data comprises at least one data unit which comprises a plurality of groups of bits;

generating a plurality of mask bits, wherein each of the plurality of mask bits is associated with one of the plurality of groups of bits; and

selectively transferring data from the computer system memory to the computer system data cache based upon given states of the plurality of mask bits.

7. The method recited in claim 6, wherein the at least one data unit comprises a cache line.

8. The method recited in claim 7, wherein each of the plurality of groups of bits comprises one byte.