Substrate subassembly and method of making transistor switch module

• US 5,492,842 A
• Filed: 01/30/1995
• Issued: 02/20/1996
• Est. Priority Date: 03/09/1994
• Status: Expired due to Term

• Current Assignee: Delphi Technologies, Inc. (Aptiv PLC)
• Original Assignee: Delco Electronics Corporation (Motors Liquidation Co. GUC Trust)
• Inventors: Martin, Timothy D., Alhoussami, Aiman I., Lachenmaier, Frank D., Lake, deceased, Donald E., Viduya, Lisa A., Tagle, John D., Eytcheson, Charles T.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Picardat, Kevin M.
• Application Number:
  US08/381,618
• Time in Patent Office: 386 Days
• Field of Search: 437/7, 437/8, 437/209, 437/211, 437/214, 437/215, 437/217, 437/218, 437/219, 437/220
• US Class Current: 438/15
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/85205 Ultrasonic bonding
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01028 Nickel [Ni]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H02M 7/003 : Constructional details, e.g. physical layout, assembly, wiring or busbar connections
• CPC Class Codes: Y10T 29/49004 : including measuring or testing of device or component part

Abstract

A substrate subassembly for a high power module, and methods involving the same. The substrate subassembly contains only one switching transistor and has at least one integral short terminal lead tab. The substrate subassemblies can be pretested at significant operating current, to obtain enhanced characterization and matching of mounted switching transistors. Trimmable gate lead resistances can be incorporated in the substrate subassemblies. Enhanced compositional, geometrical and electrical module symmetry is available. New module structures and method are afforded.

Claims

1. The method of making a high power semiconductor substrate subassembly comprising the steps of:

providing a ceramic wafer having opposed major surfaces;

forming a first metal-containing layer on a major portion of one of the major surfaces of said ceramic wafer;

forming a second metal-containing layer on a major portion of the other of said major surfaces of said ceramic wafer;

supporting only one high power insulated gate switching transistor chip on said wafer with said high power insulated gate switching transistor chip of being of pre-tested and pre-selected performance specifications and with a first active region of said transistor chip in low electrical resistance communication with said first metal-containing layer, effective to form a substrate subassembly;

disposing said subassembly on a temporary support such that heat added to said wafer by electrical operation of said transistor chip is removed into said temporary support via said second metal-containing layer;

while said substrate subassembly is disposed on said support, temporarily contacting all active regions of said transistor chip and testing said transistor chip at its intended operating power level; and

sorting said substrate subassemblies into two or more groups of operable units in accordance with performance characteristics determined by said testing.

2. The method of making a substrate subassembly as recited in claim 1 in which,

the wafer is beryllium oxide and the metal-containing layers cover each major surface of the wafer, the switching transistor chip is an insulated gate bipolar transistor, and the method further includes the steps of:

forming the metal-containing layers on the wafer by direct copper bonding copper foil to the wafer;

soldering the high power switching transistor chip to one of the copper foils to make a low electrical resistance communication with said first active region;

and clamping onto a tab of said one copper foil to make temporary electrical contact with said first active region.

3. The method of making a semiconductor switching transistor substrate subassembly as recited in claim 2 wherein the method further includes the steps of:

clamping the opposite copper foil-covered surface of the substrate subassembly against a cooling surface during testing; and

testing the one switching transistor chip on the substrate subassembly at greater than about 50% of its intended operational power rating,

to get a more representative evaluation of the performance characteristics of said switching transistor as it might exist under actual operating conditions.

4. The method of making a substrate subassembly as recited in claim 1 wherein,

the wafer is beryllium oxide, the metal-containing layers cover each major surface of the wafer, the switching transistor chip is an insulated gate bipolar transistor, and the method further includes the steps of:

forming the metal-containing layers on the wafer by direct copper bonding copper foils to opposite major faces of the wafer, one of said copper foil layers having a tab that overhangs said wafer;

applying a ceramic layer to a first surface portion of said one copper foil layer;

forming a metal-containing third layer on the ceramic layer by direct copper bonding a third copper foil to said ceramic layer, said third copper foil layer having a tab that overhangs said wafer;

soldering the switching transistor chip to a second surface portion of said one copper foil layer and establishing low electrical resistance communication between said one copper foil layer and a first active region of said switching transistor chip;

bonding one end of at least one filamentary metal wire to a second active region of said switching transistor chip and the other end to said third copper foil layer, effective to provide low electrical resistance communication between said second active region and said third copper foil layer;

providing a selected resistance unit on said subassembly;

bonding one end of at least one filamentary metal wire to a one end of a trimmable resistance and the other end to a gate electrode on said switching transistor chip, effective to provide low electrical resistance communication between said trimmable resistance and said gate electrode;

clamping onto the tab of said one copper foil to make temporary electrical contact with said first active region;

clamping onto the tab of said third copper foil to make temporary electrical contact with said second active region;

making a temporary low resistance electrical connection with the other end of said selected resistance;

clamping said substrate subassembly against a cooling surface; and

performing the testing of the one switching transistor chip on the substrate subassembly at about 100% of its intended operational power rating,

effective to obtain a representative evaluation of the performance characteristics of said switching transistor as such characteristics exist under actual operating conditions, and thereby to obtain a more representative sorting of said substrates after testing.

5. A method of making a high power semiconductor module having matched components therein comprising the steps of:

providing a plurality of ceramic wafers, each of which has opposed major surfaces;

forming a first metal-containing layer on a major portion of one of the major surfaces of each of said ceramic wafers;

forming a second metal-containing layer on a major portion of the other of said major surfaces of each of said ceramic wafers;

supporting only one high power insulated gate switching transistor chip on one of said metal-containing layers of each of said wafers, with said high power insulated gate switching transistor chip of being of pre-tested and pre-selected performance specifications, with each such switching transistor chip being soldered to the one metal-containing layer and a low electrical resistance communication being made between said one metal-containing layer and one active region of said switching transistor chip, effective to convert each substrate into a substrate subassembly;

disposing each such substrate subassembly on a temporary support that will remove heat produced in said wafer by electrical operation of said switching transistor chip;

while each said substrate subassembly is being cooled on said support, temporarily contacting said one metal-containing layer and other active regions of said switching transistor chip;

testing the switching transistor chip of each substrate subassembly at its intended electrical current rating while that substrate subassembly is being cooled on said temporary support, to determine electrical performance characteristics of said switching transistor as mounted in said substrate subassembly;

after such testing, placing each tested substrate subassembly into one of at least two groups in accordance with performance characteristics as determined in said testing;

assembling a plurality of substrate assemblies from only one of such groups into a single housing that has a power input terminal, a power output terminal, and a control terminal, with said substrate subassemblies being mounted in said housing to permit mutually cooling during operation of the switching transistors on such substrate subassemblies;

providing an electrical connection between said power input terminal and an input region of the switching transistor chip on each such substrate subassembly in said housing;

providing an electrical connection between said power output terminal and an output region of the switching transistor chip on each substrate subassembly in said housing; and

providing a control voltage from said control terminal to the switching transistor chip on each substrate subassembly.

6. A method of making a high power semiconductor module having matched components therein as recited in claim 5 wherein,

the ceramic wafers are of beryllium oxide, the metal-containing layers cover each major surface of each wafer, the switching transistor chip on each wafer is an insulated gate bipolar transistor, and the method further includes the steps of:

forming the metal-containing layers on the wafers by direct copper bonding copper foil to each major surface of each wafer;

soldering the high power switching transistor chip to one of the copper foils of each wafer to make a low electrical resistance communication with said first active region of the switching transistor;

and clamping onto a tab of said one copper foil to make temporary electrical contact with said first active region when testing the switching transistor soldered to that copper foil.

7. A method of making a high power semiconductor module having matched components therein as recited in claim 6 wherein the method further includes the steps of:

when testing any given substrate subassembly, clamping the opposite copper foil-covered surface of the substrate subassembly against a cooling surface during testing; and

testing the one switching transistor chip on that substrate subassembly at greater than about 50% of its intended operational power rating,

to get a more representative evaluation of the performance characteristics of said switching transistor chip as it might exist under actual operating conditions.

8. A method of making a high power semiconductor module having matched components therein as recited in claim 5 wherein,

the wafers are beryllium oxide and the metal-containing layers cover each major surface of each wafer, the switching transistor chip is an insulated gate bipolar transistor, and the method further includes the steps of:

forming the metal-containing layers on each wafer by direct copper bonding of copper foil to opposite major faces of each wafer, one of said layers having a tab that overhangs said wafer;

applying a ceramic layer to a first surface portion of said one copper foil layer on each wafer;

forming a metal-containing third layer on the ceramic layer of each wafer by direct copper bonding of a third copper foil to said ceramic layer, said third copper foil having a tab that overhangs said wafer;

soldering the switching transistor chip to a second surface portion of said one copper foil layer on each wafer;

soldering the switching transistor chip to a second surface portion of said one copper layer on each wafer, effective to establish low electrical resistance communication between said layer and a first active region of said switching transistor chip disposed thereon;

bonding one end of at least one filamentary metal wire to a second active region of said switching transistor chip on each wafer and the other end to said third copper foil layer, effective to provide low electrical resistance communication between said second active region and said third copper foil layer on each wafer;

providing a trimmable resistance on each substrate subassembly;

bonding one end of at least one filamentary metal wire to a one end of said trimmable resistance on each substrate subassembly and the other end to a gate electrode on said switching transistor chip, effective to provide low electrical resistance communication between said trimmable resistance and said gate electrode;

clamping onto the tab of said one copper foil layer to make temporary electrical contact with said first active region;

clamping onto the tab of said third copper foil layer to make temporary electrical contact with said second active region;

making a temporary low resistance electrical connection with the other end of said trimmable resistance;

clamping said substrate subassembly against a cooling surface; and

while making such contact and cooling said substrate assembly at a rate at least generally equal to a rate expected in normal operation, performing the testing of the one switching transistor chip on each substrate subassembly at about 100% of its intended operational power rating,

effective to obtain a more representative testing and sorting of said substrate subassemblies, and to thereby obtain closer matching of switching transistor performance in said module.