Input/output transistors with optimized ESD protection

• US 5,493,142 A
• Filed: 03/02/1995
• Issued: 02/20/1996
• Est. Priority Date: 01/12/1994
• Status: Expired due to Term

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Gongwer, Geoffrey S., Larsen, Bradley J., Randazzo, Todd A.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/397,584
• Time in Patent Office: 355 Days
• Field of Search: 257/328, 257/336, 257/344, 257/408
• US Class Current: 257/328
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An apparatus providing electrostatic discharge (ESD) protection in an input/output transistor. Disposed near the gate and the surface of the substrate is a lightly doped region. A sidewall oxide layer is selectively etched to extend laterally from a gate a significant amount. The sidewall oxide layer is also etched on an opposite side of the gate and may laterally extend an appreciable amount in that direction. A heavily doped source and drain are implanted in the substrate at areas of the surface exposed by etching, the drain separated from the gate by the significant extent of sidewall oxide. Near the surface of the substrate, the drain is separated from the gate by a similar extent of the lightly doped region, which provides a resistance in series between the drain and gate for ESD protection. The source may also be separated from the gate by a lightly doped region of appreciable extent, which acts as a series resistance between the source and the gate to mitigate ESD. The extent of the sidewall oxide, and thus the lightly doped regions separating the gate from the drain and source, can be tailored to optimize ESD protection and performance characteristics for a given application by defocusing snapback conduction.

Claims

1. An electrostatic discharge protection device for an integrated circuit chip comprising:

a semiconductor substrate with a terminal for communication external to the substrate disposed thereon,

a discharge structure disposed in said substrate having heavily doped regions of a first conductivity type forming a source and a drain with a channel of a second conductivity type disposed therebetween, said drain connected to said terminal and said source disposed distal to said terminal, said structure being characterized by a trigger voltage above which snapback conduction along a path between said source and said drain is initiated, a holding voltage above which said snapback conduction is sustained, and a maximum nondestructive current density along said path,

a lightly doped region of said first conductivity type forming a drain extension separating said drain and said channel and having a resistance in series with said path such that a flow of said maximum nondestructive current density along said path creates a voltage between said source and said drain along said path exceeding said trigger voltage, initiating snapback conduction in an adjacent path between said source and said drain.

2. The device of claim 1 wherein said maximum nondestructive current density integrated over an area of said channel traversed by said paths is greater than a current through said terminal from an electrostatic discharge event.

3. The device of claim 1 wherein said channel is characterized by a channel resistivity (ρ

_c) during said snapback conduction and has a length (L_c) separating said source and said drain extension, wherein said drain extension is characterized by a resistivity (ρ

_d) and has an extent (E_d) separating said drain from said channel, and

space="preserve" listing-type="equation">E.sub.d ≧

[V.sub.t -V.sub.H -I.sub.m ρ

.sub.c L.sub.c ]/I.sub.m ρ

p.sub.d

wherein V_t is said trigger voltage, V_H is said holding voltage and I_m is said maximum current density.

4. The device of claim 1 and further comprising a gate separated from said channel by a gate oxide characterized by a maximum nondestructive voltage, wherein a difference between said maximum nondestructive gate oxide voltage and said holding voltage is greater than a difference in voltage between said source and said drain along said paths of an electrostatic discharge current multiplied by a resistance along said paths and divided by a difference between said trigger voltage and said holding voltage.

5. The device of claim 1 wherein said channel has a generally orthogonally related length, width and depth, said length separating said source and said drain extension and said depth encompassing a flow of said snapback current measured from a surface of said substrate, said width being many times larger than said length and said depth, and wherein a current from an electrostatic discharge event is less than said maximum nondestructive current density integrated over said width and said depth.

6. The device of claim 1 wherein said structure comprises an input/output transceiver.

7. The device of claim 1 wherein said structure comprises an output buffer.

8. The device of claim 1 wherein said structure comprises an input buffer.

9. The device of claim 1 and further comprising a gate separated from said channel by a gate oxide, wherein said drain extension has an extent between said drain and said channel that is greater than a height of a top of said gate from said channel.

10. The device of claim 1 wherein said drain extension has an extent between said drain and said channel at least as large as a length of said channel between said source and said drain extension.

11. The device of claim 1 wherein said drain extension has an extent between said drain and said channel that is greater than three-tenths of a micron and less than six microns.

12. The device of claim 1 wherein said drain extension has a doping concentration in a range between 10¹⁷ ions/cm³ and 5×

10¹⁹ ions/cm³.

13. An electrostatic discharge tolerant device for communication between an integrated circuit chip and a circuit external to the chip comprising:

a semiconductor chip with a surface having a bond pad disposed thereon,

a transistor having heavily doped subsurface source and drain regions separated by a channel region, with a gate disposed over said channel region and separated from said surface by a gate oxide layer, said drain region connected with said bond pad, a lightly doped drain extension disposed between said channel and said drain region,

a path between said source region and said drain region characterized by a trigger voltage initiating snapback conduction across said channel, a holding voltage sustaining said snapback conduction and a maximum nondestructive current density,

wherein said drain extension has a resistance in series with said path such that a flow of said maximum nondestructive current density along said path raises a voltage of said path above said trigger voltage, thereby initiating snapback conduction in an adjacent path.

14. The device of claim 13 wherein said channel has a length oriented along said paths and a width oriented transversely to said paths, said width being many times larger than said length such that an electrostatic discharge current distributed uniformly across said width has a current density less than said maximum nondestructive current density.

15. The device of claim 14 wherein said drain extension has an extent (E_d) oriented along said paths, and

16. The device of claim 14 wherein said gate oxide layer is characterized by a maximum nondestructive voltage (V_g), and

17. The device of claim 13 and further comprising a sidewall oxide layer adjoining said gate and said drain extension, said sidewall oxide layer extending along said surface a distance from said gate oxide greater than a height of a top of said gate from said surface.

18. The device of claim 13 wherein said drain extension has an extent along said paths greater than 0.4 microns and less than 3.0 microns.

19. The device of claim 13 wherein said drain extension has a sheet resistance in a range between 100 and 5,000 Ohms/square.

20. An input/output device for transmitting signals between an integrated circuit chip and a circuit external to the chip comprising:

a semiconductor substrate having a surface and a bond pad adjacent to said surface for communication between a circuit of said substrate and a circuit external to said substrate,

an active region of said substrate having doped sections near said surface forming a source and a drain of a first conductivity type separated by a channel of a second conductivity type, said drain connected to said bond pad,

a gate having a bottom disposed adjacent to said channel and separated from said surface by a gate oxide layer, said gate having a top distal to said surface,

a drain sidewall oxide layer disposed on said surface adjacent to said gate oxide layer and said drain and extending a distance along said surface away from said gate that is greater than a height of said top of said gate from said surface,

a lightly doped extension of said drain adjoining said drain sidewall oxide layer and said channel along said distance.

21. The device of claim 20 and further comprising:

a source sidewall oxide layer disposed on said surface adjacent to said gate oxide layer and said source and extending along said surface away from said gate a span that is greater than said height of said top of said gate from said surface, and

a lightly doped portion of said source adjoining said source sidewall oxide layer and said channel along said width and said span.

22. The device of claim 20 wherein said channel is characterized by a maximum nondestructive current density and said lightly doped portion of said drain spreads snapback current along a width and depth of said channel, and wherein an area formed by said width multiplied by said depth is greater than an electrostatic current pulse divided by said maximum nondestructive current density.

23. The device of claim 20 being characterized by a trigger voltage above which snapback conduction along a path between said source and said drain is initiated, a holding voltage above which said snapback conduction is sustained, and a maximum nondestructive current density along said path, wherein said drain extension separating said drain and said channel has a resistance in series with said path such that a flow of said maximum nondestructive current density along said path creates a voltage over said path exceeding said trigger voltage, initiating snapback conduction in an adjacent path between said source and said drain.

24. The device of claim 23 wherein said gate oxide layer is characterized by a maximum nondestructive voltage that is greater than said trigger voltage.