System powered with inter-coupled charge pumps

• US 5,493,249 A
• Filed: 12/06/1993
• Issued: 02/20/1996
• Est. Priority Date: 12/06/1993
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A.
• Primary Examiner(s): CUNNINGHAM, TERRY D
• Application Number:
  US08/164,163
• Time in Patent Office: 806 Days
• Field of Search: 307/264, 307/296.1, 307/296.2, 307/296.4, 307/296.6, 307/578, 327/306, 327/323, 327/331, 327/390, 327/538, 327/540, 327/541, 327/543, 327/545, 327/546
• US Class Current: 327/540
• CPC Class Codes: G05F 3/24 wherein the transistors are of the field-effect type only G05F3/205, G05F3/26, G05F3/30 take precedence
• CPC Class Codes: G05F 3/242 with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type

Abstract

A multi-phase charge pump continuously pumps to establish a DC voltage outside the range of supply and reference voltages according to the apparatus and methods of the present invention. The multi-phase charge pump in one embodiment includes four stages operating in a ring with a four-phase clock. Each stage includes a three-mode charge pump that generates and provides reset and control signals to other stages. Each stage includes a pass transistor having a gate driven in excess of the DC voltage for efficient transfer of charge. The gate drive signal from a first stage is coupled to a next stage in the ring where it is used to generate the next gate drive signal. Each gate drive signal corresponds to one waveform having a phase skewed in time so that each stage in the ring is operating in a different mode. According to a method of the present invention, a first stepped voltage is developed on a first capacitor and selectively coupled to a second capacitor to develop a second stepped voltage of greater absolute value. The second stepped voltage gates charge transfer from a first stage and enables the selective coupling in a next stage in a sequence of pump stages.

Claims

1. An integrated circuit comprising:

a. an operational circuit; and

b. a voltage generator electrically coupled to the operational circuit for providing electrical power, the voltage generator comprising a plurality of charge pumps, wherein each charge pump supplies power to the operational circuit during a portion of a duty cycle, and wherein each pump selectively enables a next charge pump of the plurality to supply power to the operational circuit during a next portion of the duty cycle, each charge pump including;

(i) a first means for storing an electrical voltage in response to a first input signal voltage;

(ii) a second means for storing an electrical voltage in response to a second input signal voltage;

(iii) a first switching means for electrically coupling the first storage means and the second storage means to create a shared voltage, the switching means being activated when the voltage of a third input signal reaches an activation level;

a third means for storing an electrical charge;

(v) a second switching means for electrically coupling the third storage means with the operational circuit, the second switching means being activated when the shared voltage of the first storage means and the second storage means reaches a desired value, wherein the value of the shared voltage over time produces a third input signal for a next charge pump.

2. The integrated circuit of claim 1 wherein each third storage means provides a substrate bias for the operational circuit.

3. The integrated circuit of claim 1 wherein:

a. the voltage generator receives a reference signal having a first voltage level, and a power signal having a second voltage level; and

b. the voltage across each third storage means is outside the range from the first voltage level to the second voltage level when each third storage means is coupled to the operational circuit.

4. An integrated circuit comprising a voltage generator and an operational circuit, the operational circuit powered by the voltage generator, the operational circuit for performing a function of the integrated circuit, the voltage generator comprising:

a. an oscillator;

b. a plurality of pump circuits inter-coupled in a sequence having prior and next relations among pump circuits of the sequence so that a pump circuit of the sequence receives a first timing signal from a prior pump circuit of the sequence, and provides a second timing signal to a next pump circuit of the sequence, and so that the pump circuit, responsive to the oscillator, supplies power to the operational circuit at a first time and enables the next pump circuit, responsive to the second timing signal, to supply power to the operational circuit at a second time, wherein the pump circuit of the sequence comprises;

(1) a first storage means for storing a first charge;

(2) a control means, responsive to tile first timing signal, for providing the second timing signal; and

(3) a transfer means, responsive to the first timing signal, for electrically coupling the first storage means to the operational circuit, thereby supplying power to the operational circuit.

5. The integrated circuit of claim 4 wherein the transfer means is further responsive to the second timing signal for electrically coupling the first storage means to the operational circuit.

6. The integrated circuit of claim 4 wherein the voltage generator receives a reference signal having a first voltage level and receives a power signal having a second voltage level, and the transfer means comprises:

a. pass means for selectively conducting charge between the first storage means and the operational circuit when enabled by a control signal;

b. a first voltage source means for providing a third voltage;

c. a second voltage source means; and

d. coupling means, responsive to the first timing signal, for selectively coupling the first voltage source means to the second voltage source means for providing the control signal.

7. The integrated circuit of claim 6 wherein the control signal is characterized by having a voltage outside the range from the first voltage level to the second voltage level.

8. The integrated circuit of claim 6 wherein the pump circuit receives a third timing signal from a pump circuit prior to the prior pump circuit of the sequence, and the first voltage source means is responsive to the third timing signal.

9. The integrated circuit of claim 6 wherein:

a. the integrated circuit further comprises a clocking means, coupled in series between the oscillator and the pump circuit, for generating a first clock signal in response to a signal from tile oscillator; and

b. the second voltage source means is responsive to the first clock signal.

10. The integrated circuit of claim 9 wherein:

a. the transfer means further comprises reset means for establishing an initial charge on the first storage means; and

b. the clocking means generates a second clock signal for enabling the reset means.

11. The integrated circuit of claim 10 wherein the second clock signal is coupled to a next pump circuit of the next pump circuit of the sequence for enabling the transfer means of said next pump circuit of the next pump circuit.

12. An integrated circuit comprising:

a. an operational circuit;

b. a timing circuit for providing a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal;

c. a first charge pump for supplying power to the operational circuit at a first time in response to the first clock signal, and for providing a first reset signal and a first control signal;

d. a second charge pump for supplying power to the operational circuit at a second time in response to tile second clock signal and the first control signal, and for providing a second reset signal and a second control signal;

e. a third charge pump, initialized in response to the first reset signal, for supplying power to tile operational circuit at a third time in response to the third clock signal and the second control signal, and for providing a third reset signal and a third control signal;

f. a fourth charge pump, initialized in response to the second reset signal, for supplying power to the operational circuit at a fourth time in response to the fourth clock signal and the third control signal, and for providing a fourth reset signal and a fourth control signal;

g. wherein the first charge pump is initialized in response to the third reset signal and supplies power in further response to the fourth control signal; and

h. wherein the second charge pump is initialized in response to the fourth reset signal.

13. A method for powering a circuit, the method comprising the steps of:

charging a first storage means;

coupling the first storage means to a pass transistor for selective conduction to the circuit, the pass transistor having a control terminal;

charging a second storage means;

charging a third storage means

coupling the second storage means to the third storage means to develop a stepped voltage;

and

coupling the stepped voltage to the control terminal of the pass transistor, thereby selectively enabling the first storage means to power the circuit.