High efficiency compact low power voltage doubler circuit
First Claim
Patent Images
1. A voltage doubler circuit, comprising;
- an inverter circuit including an input and an output;
a complementary switch pair circuit including a N-channel transistor having a gate, drain and source and a P-channel transistor having a gate, drain and source, the gates of the N-channel transistor and the P-channel transistor being connected defining a common gate connection, the sources of the N-channel transistor and the P-channel transistor being connected defining a common source connection, whereby the P-channel transistor, the N-channel transistor and the inverter can be substantially simultaneously switched and the current drain is substantially minimized;
the input of the inverter circuit being coupled to the common gate connection via a coupling capacitor;
the output of the inverter circuit being coupled to the common source connection via a charge-pump capacitor; and
a DC biasing circuit being connected to the common gate connection, the DC biasing circuit for supplying a signal to the common gate connection, whereby the DC biasing circuit initially charges the coupling capacitor to a DC bias level and thereafter, under steady state conditions, compensates leakage currents present at the common gate connection.
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Abstract
What is described is a high efficiency voltage doubler (100). The high efficiency voltage doubler (100), has a charge-pump capacitor (30), an inverter (18), a coupling capacitor (24), a complementary switch pair (16), a DC biasing circuit (102), a charging circuit (106), and an input circuit (108). This structure is adapted for use in an integrated circuit, and provides the advantage of maximizing voltage doubled power output and minimizing current consumption with a minimal number of components.
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Citations
21 Claims
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1. A voltage doubler circuit, comprising;
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an inverter circuit including an input and an output; a complementary switch pair circuit including a N-channel transistor having a gate, drain and source and a P-channel transistor having a gate, drain and source, the gates of the N-channel transistor and the P-channel transistor being connected defining a common gate connection, the sources of the N-channel transistor and the P-channel transistor being connected defining a common source connection, whereby the P-channel transistor, the N-channel transistor and the inverter can be substantially simultaneously switched and the current drain is substantially minimized; the input of the inverter circuit being coupled to the common gate connection via a coupling capacitor; the output of the inverter circuit being coupled to the common source connection via a charge-pump capacitor; and a DC biasing circuit being connected to the common gate connection, the DC biasing circuit for supplying a signal to the common gate connection, whereby the DC biasing circuit initially charges the coupling capacitor to a DC bias level and thereafter, under steady state conditions, compensates leakage currents present at the common gate connection. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A voltage doubler circuit, comprising:
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a first inverter circuit including an input and an output; a complementary switch pair circuit including a N-channel transistor having a gate, drain and source and a P-channel transistor having a body, gate, drain and source, the gates of the N-channel transistor and the P-channel transistor being connected defining a common gate connection, the sources of the N-channel transistor and the P-channel transistor being connected defining a common source connection, whereby the P-channel transistor, the N-channel transistor and the first inverter circuit can be substantially simultaneously switched and the current drain is substantially minimized; the input of the first inverter circuit being coupled to the common gate connection via a coupling capacitor; the output of the first inverter circuit being coupled to the common source connection via a charge-pump capacitor; and a biasing circuit being connected to the body of the complementary switch pair P-channel transistor, the biasing circuit driving the body of the complementary switch pair P-channel transistor to a predetermined potential substantially the same as that of the drain of the complementary switch pair P-channel transistor, whereby a potential between any of the gate, drain, source and body of the complementary switch pair P-channel transistor substantially never exceeds a voltage greater than a positive supply voltage which allows for a lower voltage, higher current transistor design.
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10. A voltage doubler circuit, comprising:
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a first inverter circuit including an input and an output; a complementary switch pair circuit including a N-channel transistor having a gate, drain and source and a P-channel transistor having a body, gate, drain and source, the gates of the N-channel transistor and the P-channel transistor being connected defining a common gate connection, the sources of the N-channel transistor and the P-channel transistor being connected defining a common source connection, whereby the P-channel transistor, the N-channel transistor and the first inverter circuit can be substantially simultaneously switched and the current drain is substantially minimized; the input of the first inverter circuit being coupled to the common gate connection via a coupling capacitor; the output of the first inverter circuit being coupled to the common source connection via a charge-pump capacitor; and a biasing circuit including a biasing capacitor and a P-channel biasing transistor having a body, gate, drain and source, the source of the P-channel biasing transistor being connected to the common source connection, the gate of the P-channel biasing transistor being connected to the common gate connection, the biasing capacitor and the drain and body of the P-channel biasing transistor being connected to the body of the complementary switch pair P-channel transistor; and the biasing circuit driving the body of the complementary switch pair P-channel transistor to a predetermined potential substantially the same as that of the drain of the complementary switch pair P-channel transistor, whereby a potential between any of the gate, drain, source and body of the complementary switch pair P-channel transistor substantially never exceeds a voltage greater than a positive supply voltage which allows for a lower voltage, higher current transistor design. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification