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High efficiency compact low power voltage doubler circuit

  • US 5,493,486 A
  • Filed: 03/17/1995
  • Issued: 02/20/1996
  • Est. Priority Date: 03/17/1995
  • Status: Expired due to Fees
First Claim
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1. A voltage doubler circuit, comprising;

  • an inverter circuit including an input and an output;

    a complementary switch pair circuit including a N-channel transistor having a gate, drain and source and a P-channel transistor having a gate, drain and source, the gates of the N-channel transistor and the P-channel transistor being connected defining a common gate connection, the sources of the N-channel transistor and the P-channel transistor being connected defining a common source connection, whereby the P-channel transistor, the N-channel transistor and the inverter can be substantially simultaneously switched and the current drain is substantially minimized;

    the input of the inverter circuit being coupled to the common gate connection via a coupling capacitor;

    the output of the inverter circuit being coupled to the common source connection via a charge-pump capacitor; and

    a DC biasing circuit being connected to the common gate connection, the DC biasing circuit for supplying a signal to the common gate connection, whereby the DC biasing circuit initially charges the coupling capacitor to a DC bias level and thereafter, under steady state conditions, compensates leakage currents present at the common gate connection.

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