Integrated circuit device and method of designing same

• US 5,493,506 A
• Filed: 09/14/1993
• Issued: 02/20/1996
• Est. Priority Date: 01/14/1993
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Hashizume, Takeshi, Sakashita, Kazuhiro, Komoike, Tatsunori, Yusa, Terukazu, Takimoto, Isao
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): MCFADDEN, SUSAN IRIS
• Application Number:
  US08/120,390
• Time in Patent Office: 889 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/121
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits

Abstract

A register circuit an arithmetic circuit a register circuit and a logic circuit form a bit slice cell corresponding to a path of propagation connecting the circuits in this order. Similarly, an arithmetic circuit register circuits and a logic circuit form a bit slice cell and an arithmetic circuit register circuits and a logic circuit form a bit slice cell. The bit slice cells are arranged generally in parallel to form a bit slice circuit which prevents redundant lines for connecting the functional circuits, whereby the bit slice circuit is developed in a short period without a decreased degree of integration and prolonged delay time.

Claims

1. An integrated circuit device comprising:

a plurality of bit slice cells,

each of said bit cells including at least one functional circuit for achieving a predetermined function,

said at least one functional circuit in each of said bit slice cells being arranged in at least one row and interconnected,

said integrated circuit device being divided into a first region in which said bit slice cells are placed and a second region surrounding said first region, and

said integrated circuit device further comprising a drive line surrounding said first region in said second region and used for driving said functional circuits.

2. The integrated circuit device of claim 1, wherein said at least one functional circuit is arranged in a plurality of rows in at least one of said bit slice cells.

3. The integrated circuit device of claim 1, wherein said drive line is a power supply line for supplying power source to said functional circuits.

4. The integrated circuit device of claim 3, further comprising:

a first power source trunk line provided in said first region and connected to said power supply line at a connecting point; and

a second power source trunk line provided in said second region and connected to said power supply line at said connecting point.

5. The integrated circuit device of claim 3, further comprising:

a first power source trunk line provided in said first region and connected to said power supply line at a first connecting point; and

a second power source trunk line provided in said second region and connected to said power supply line at a second connecting point different from said first connecting point.

6. The integrated circuit device of claim 1, wherein said drive line is a clock line for supplying a clock signal to said functional circuits.

7. The integrated circuit device of claim 6, further comprising:

a first clock trunk line provided in said first region and connected to said clock line at a connecting point; and

a second clock trunk line provided in said second region and connected to said clock line at said connecting point.

8. The integrated circuit device of claim 6, further comprising:

a first clock trunk line provided in said first region and connected to said clock line at a first connecting point; and

a second clock trunk line provided in said second region and connected to said clock line at a second connecting point different from said first connecting point.

9. The integrated circuit device of claim 1, wherein said at least one functional circuit is arranged in a row in each of said bit slice cells.

10. The integrated circuit device of claim 9, wherein at least one of said functional circuits is an arithmetic circuit for performing an arithmetic operation in at least one of said bit slice cells.

11. The integrated circuit device of claim 10, wherein at least one of said functional circuits is a register circuit for holding data in at least one of said bit slice cells.

12. The integrated circuit device of claim 11, wherein at least one of said functional circuits is a logic circuit for performing a logic processing on data in at least one of said bit slice cells.

13. The integrated circuit device of claim 9, wherein said functional circuits which achieve the same function form a functional block, and

said functional circuits are arranged in a column for each functional block.

14. The integrated circuit device of claim 13,

said integrated circuit device being divided into a first region in which said bit slice cells are placed and a second region different from said first region,

said integrated circuit device further comprising:

a connecting line; and

a memory circuit connected to said functional circuits with said connecting connecting line is minimized.

15. The integrated circuit device of claim 14, wherein said memory circuit includes a ROM.

16. The integrated circuit device of claim 15, wherein

said ROM has at least a first connecting terminal connected to said connecting line,

said integrated circuit device further comprising:

at least a second connecting terminal corresponding to said at least first connecting terminal provided on the boundary between said first and second regions for connecting said connecting line and said functional circuits to each other,

each of said at least a first and a second connecting terminals being aligned in first and second, rows, respectively.

17. The integrated circuit device of claim 16, wherein said first and second terminals are aligned in opposed relation to each other.

18. The integrated circuit device of claim 14, wherein said memory circuit includes a PLA.

19. The integrated circuit device of claim 18, wherein said PLA has a first connecting terminal connected to said connecting line,

said integrated circuit device further comprising:

a second connecting terminal corresponding to said first connecting terminal provided on the boundary between said first and second regions for connecting said connecting line and said functional circuits to each other,

said first and second connecting terminals being aligned in first and second, opposed rows, respectively.

20. The integrated circuit device of claim 19, wherein said first and second terminals are opposed to each other.

21. The integrated circuit device of claim 14, wherein

said second region surrounds said first region,

said integrated circuit device further comprising a power supply line surrounding said first region in said second region for supplying power source to said memory circuit.

22. The integrated circuit device of claim 21, wherein said memory circuit includes a ROM.

23. The integrated circuit device of claim 21, wherein said memory circuit includes a PLA.

24. The integrated circuit device of claim 21, further comprising:

a first power source trunk line provided in said first region and connected to said power supply line at a connecting point; and

a second power source trunk line provided in said second region and connected to said power supply line at said connecting point.

25. The integrated circuit device of claim 21, further comprising:

a first power source trunk line provided in said first region and connected to said power supply line at a first connecting point; and

a second power source trunk line provided in said second region and connected to said power supply line at a second connecting point different from said first connecting point.

26. The integrated circuit device of claim 1, further comprising

a clock driver for driving said functional circuits,

said integrated circuit device being divided into a first region in which said bit slice cells are placed and a second region in which said clock driver is placed.

27. The integrated circuit device of claim 26, wherein

said functional circuit is arranged in a row in each of said bit slice cells, and

said clock driver is provided in corresponding relation to said bit slice cells.

28. The integrated circuit device of claim 26, wherein

said functional circuits which achieve the same function form a functional block,

said functional circuits are arranged in a column for each functional block, and

said clock driver is provided in corresponding relation to said functional blocks.

29. A method of designing an integrated circuit device, comprising the steps of:

(a) specifying a predetermined range;

(b) placing a connecting terminal at an edge of said predetermined range;

(c) placing a plurality of bit slice cells generally in parallel in said predetermined range, each of said bit cells including at least one functional circuit for achieving a predetermined function;

(d) placing one of said functional circuits in a first one of said bit slice cells to determine routing of wiring in said first bit slice cell;

(e) placing another one of said functional circuits in an N-th one of said bit slice cells (where N is an integer more than

     1) in consideration for placement and routing information of said functional circuit of an M-th one of said bit slice cells (where M is a natural number less than N) to determine routing of wiring in said N-th bit slice cell; and

(f) determining routing of wiring between said functional circuits.

30. A method of designing an integrated circuit device, comprising the steps of:

(a) making a logic design for an integrated circuit performing a predetermined processing to determine a logic design circuit;

(b) dividing said logic design circuit into units of said predetermined processing to determine a plurality of bit slice cells each having at least one functional circuit for achieving a predetermined function;

(c) placing one of said functional circuits in a first one of said bit slice cells to determine routing of wiring in said first bit slice cell

(d) placing another one of said functional circuits in an N-th one of said bit slice cells (where N is an integer more than

     1) in consideration for placement and routing information of said functional circuit of an M-th one of said bit slice cells (where M is a natural number less than N) to determine routing of wiring in said N-th bit slice cell; and

(e) determining routing of wiring between said functional circuits.

31. The method of claim 30, wherein

said M is equal to 1.

32. A method of designing an integrated circuit device, comprising the steps of:

(a) making a logic design for an integrated circuit performing a predetermined processing to determine a logic design circuit;

(b) dividing said logic design circuit into functional circuits each for achieving a predetermined function;

(c) specifying a predetermined region;

(d) dividing said predetermined region into units of said predetermined processing to determine bit regions;

(e) placing said functional circuits across said plurality of said bit regions; and

(f) determining routing of wiring between said functional circuits.

33. A method of designing an integrated circuit device, comprising the steps of:

(a) making a logic design for an integrated circuit performing a predetermined processing to determine a logic design circuit;

(b) dividing said logic design circuit to determine a plurality of functional circuit blocks each including at least one functional circuit for achieving the same function;

(c) specifying a predetermined region;

(d) dividing said predetermined region into units of said predetermined processing to determine bit regions;

(e) placing said functional circuit blocks across at least two of said bit regions; and

(f) determining routing of wiring between said functional circuits.

34. The method of claim 33, wherein said step (b) includes the step of:

(b-1) dividing said functional circuit blocks into units of said predetermined processing, and

said step (c) includes the step of;

(c-1) placing said functional circuits in said bit regions, respectively, in accordance with said processing units.