Integrated circuit memory with disabled edge transition pulse generation during special test mode
First Claim
1. An integrated memory circuit, having a normal operating mode and a special test mode, comprising:
- a plurality of memory cells, arranged in rows and columns;
a plurality of input terminals;
circuitry for selecting one of said plurality of memory cells responsive to an address signal received at said plurality of input terminals;
edge transition detection circuitry, coupled to said plurality of input terminals, for initiating a memory operation responsive to detecting a logic transition at said plurality of input terminals;
test mode enable circuitry for generating a test mode enable signal responsive to receiving a test mode select signal; and
a gating circuit, coupled to said test mode enable circuitry and to the edge transition detection circuitry, for inhibiting said edge transition detection circuitry from initiating the memory operation responsive to said test mode enable signal.
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Accused Products
Abstract
An integrated memory circuit having special stress test mode capability, and that is safely controlled by edge transition detection, is disclosed. The memory includes a test mode enable circuit that generates a test mode enable signal responsive to receiving overvoltage signals or other codes at terminals of the memory; the test mode enable signal is presented to the edge transition detection circuitry, so that the edge transition detection pulse that would otherwise initiate a memory operation is not generated during special test mode. This prevents the disastrous possibility that memory functions would be initiated by false edge transition detection signals (such as may occur during ramping of supply voltages to stress levels) during the special test mode. Special tests, such as stress tests and long write cycle disturb tests, may thus be safely performed.
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Citations
21 Claims
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1. An integrated memory circuit, having a normal operating mode and a special test mode, comprising:
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a plurality of memory cells, arranged in rows and columns; a plurality of input terminals; circuitry for selecting one of said plurality of memory cells responsive to an address signal received at said plurality of input terminals; edge transition detection circuitry, coupled to said plurality of input terminals, for initiating a memory operation responsive to detecting a logic transition at said plurality of input terminals; test mode enable circuitry for generating a test mode enable signal responsive to receiving a test mode select signal; and a gating circuit, coupled to said test mode enable circuitry and to the edge transition detection circuitry, for inhibiting said edge transition detection circuitry from initiating the memory operation responsive to said test mode enable signal. - View Dependent Claims (2, 3, 5, 6, 7, 8, 9, 21)
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4. An integrated memory circuit, having a normal operating mode and a special test mode, comprising:
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a plurality of memory cells, arranged in rows and columns; a plurality of address terminals, for receiving an address signal; a plurality of data terminals; a control terminal; circuitry for selecting one of said plurality of memory cells responsive to the address signal received at said plurality of address terminals; edge transition detection circuitry, coupled to said plurality of address terminals and to said plurality of data terminals, for initiating a memory operation responsive to detecting a logic transition at one or more of said plurality of address terminals or data terminals; and test mode enable circuitry for generating a test mode enable signal responsive to receiving a test mode select signal; wherein said edge transition detection circuitry is coupled to said test mode enable circuitry to receive the test mode enable signal, so that said edge transition detection circuitry is inhibited from initiating the memory operation responsive to said test mode enable signal.
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10. A method of operating an integrated circuit that includes a memory having a normal operating mode and a special test mode, comprising the steps of:
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monitoring a plurality of input terminals to detect a logic level transition thereat; responsive to detecting a logic level transition at one of the plurality of input terminals, initiating a memory operation; receiving a test mode select signal; responsive to receiving the test mode select signal, initiating the special test mode for the memory; and responsive to receiving the test mode select signal, inhibiting the initiation of the memory operation responsive to detecting the logic level transition at one of the plurality of input terminals. - View Dependent Claims (11, 12, 14, 15, 16, 17, 18, 19, 20)
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13. A method of operating an integrated circuit that includes a memory having a normal operating mode and a special test mode, comprising the steps of:
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monitoring a plurality of address terminals and data terminals to detect a logic level transition thereat; responsive to detecting a logic level transition at one of the plurality of address terminals or data terminals, initiating a memory operation; receiving a test mode select signal; responsive to receiving the test mode select signal, initiating the special test mode for the memory; and responsive to receiving the test mode select signal, inhibiting the initiation of the memory operation responsive to detecting a logic level transition at one of the plurality of address and data terminals.
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Specification