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Integrated circuit memory with disabled edge transition pulse generation during special test mode

  • US 5,493,532 A
  • Filed: 05/31/1994
  • Issued: 02/20/1996
  • Est. Priority Date: 05/31/1994
  • Status: Expired due to Term
First Claim
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1. An integrated memory circuit, having a normal operating mode and a special test mode, comprising:

  • a plurality of memory cells, arranged in rows and columns;

    a plurality of input terminals;

    circuitry for selecting one of said plurality of memory cells responsive to an address signal received at said plurality of input terminals;

    edge transition detection circuitry, coupled to said plurality of input terminals, for initiating a memory operation responsive to detecting a logic transition at said plurality of input terminals;

    test mode enable circuitry for generating a test mode enable signal responsive to receiving a test mode select signal; and

    a gating circuit, coupled to said test mode enable circuitry and to the edge transition detection circuitry, for inhibiting said edge transition detection circuitry from initiating the memory operation responsive to said test mode enable signal.

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