Remotely re-programmable program memory for a microcontroller

• US 5,493,534 A
• Filed: 05/17/1995
• Issued: 02/20/1996
• Est. Priority Date: 07/29/1993
• Status: Expired due to Term

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Mok, Tsung D.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/443,237
• Time in Patent Office: 279 Days
• Field of Search: 365/226, 365/218, 365/189.01, 365/230.01, 365/94, 365/900
• US Class Current: 365/185.33
• CPC Class Codes: G06F 15/7814 Specially adapted for real time processing, e.g. comprising hardware timers
• CPC Class Codes: G06F 9/24 Loading of the microprogram
• CPC Class Codes: G06F 9/4403 Processor initialisation
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/30 Power supply circuits

Abstract

A single chip microcontroller has a plurality of I/O ports which communicate directly and indirectly with an electrically programmable and erasable read only memory array used as a program store circuit. The PEROM array provides for fast erasing and reprogramming, either directly from a local host or remotely. The plurality of ports provides alternative access routes to the memory store, thereby providing a capability for verifying microinstructions immediately after writing them, one at a time. A random access memory, RAM, is also provided. The PEROM array is like hard disk storage in a microcontroller. A low voltage power supply has a connected charge pump which provides a programming and erase high voltage for the PEROM array.

Claims

1. A re-programmable memory system with a microcontroller comprising,

a remote host computer having a memory store with updated programs for execution by field microcontrollers,

a single chip microcontroller having a single low voltage power supply, the microcontroller electrically communicating with said remote host computer and having electrically programmable and erasable read only memory cells and RAM memory cells, the electrically programmable and erasable read only memory cells connected as a main program store having power conversion means to generate voltage levels necessary for clearing the electrically programmable and erasable read only memory cells and writing therein using the low voltage power supply.

2. A re-programmable memory system with a microcontroller comprising,

a remote host computer having a memory store with updated programs for execution by field microcontrollers,

a single chip microcontroller having a single low voltage power supply, the microcontroller electrically communicating with said remote host computer and having PEROM and RAM memory cells, the PEROM memory cells connected as a main program store having power conversion means for clearing the PEROM cells and writing therein using the low voltage power supply, said power conversion means comprises a multi-stage charge pump having a low voltage input and a high voltage output and a clamp circuit means for holding the high voltage on command.

3. A re-programmable memory system with a microcontroller comprising,

a remote host computer having a memory store with updated programs for execution by field microcontrollers,

a single chip microcontroller having a single low voltage power supply, the microcontroller electrically communicating with said remote host computer and having PEROM and RAM memory cells, the PEROM memory cells connected as a main program store having power conversion means for clearing the PEROM cells and writing therein using the low voltage power supply, said power conversion means comprises a multi-stage charge pump having a low voltage input and a high voltage output and a discharge circuit means for discharging the high voltage on command.

4. A program store circuit arrangement in an integrated circuit microcontroller of the type having an arithmetic logic unit, a plurality of registers associated with the arithmetic unit for executing program instructions and operating on data comprising,

an array of electrically programmable and erasable read only memory transistors arranged in blocks whereby blocks of transistors may be simultaneously erased,

an address bus connected to said array, said address bus in bidirectional communication with a port capable of receiving microinstructions from an external source,

a data bus connected to said array as an output in a unidirectional manner and connected to microcontroller circuits on the data bus whereby said array is isolated from direct receipt of data from the data bus but communicates outwardly to the microcontroller circuits on the data bus,

a random access memory array connected to the data bus,

a bidirectional buffer separating the address bus from the data bus but permitting communication therebetween,

a plurality of bidirectional I/O port means for bidirectional exchange of program address and data information, and

a low voltage power supply having a connected charge pump means for converting the low voltage supply to a voltage level adequate for programming and erasing the electrically programmable and erasable read only memory transistors.

5. The circuit arrangement of claim 4 wherein the array of electrically programmable and erasable read only memory transistors comprise storage cells of two transistors including a select transistor and a bit storage transistor, both transistors operable from a single low voltage source.

6. The circuit arrangement of claim 5 wherein the bit storage transistor comprises a sense gate and a floating gate, the floating gate disposed over a region of thin tunnel oxide.

7. The circuit arrangement of claim 4 wherein said plurality of bidirectional I/O port means comprises,

first and second bidirectional I/O port means connected to the address bus and the data bus for communication with an external program and data memory, and

a third bidirectional I/O port means connected to the data bus for sharing tasks of the first and second port means.

8. In a microcontroller having an arithmetic logic unit, an accumulator and registers feeding the arithmetic logic unit, bidirectional I/O ports, an address bus and a data bus, the program store circuit improvement comprising,

an array of electrically programmable and erasable read only memory transistors arranged in blocks whereby blocks of transistors may be simultaneously erased, the array connected to microcontroller circuits via the address and data buses,

an array of random access memory transistors connected to the microcontroller circuits via the address and data buses, and

a low voltage power supply having a connected charge pump means for converting the low voltage supply to a voltage level which programs and erases the electrically programmable and erasable read only memory transistors.

9. The microcontroller of claim 8 wherein the array of electrically programmable and erasable memory transistors comprise a flash transistor array.

10. The microcontroller of claim 8 wherein the array of electrically programmable and erasable memory transistors comprise storage cells of two transistors including a select transistor and a bit storage transistor, both transistors operable from a single low voltage source.

11. The microcontroller of claim 8 wherein the bit storage transistor comprises a sense gate and a floating gate, the floating gate disposed over a region of thin tunnel oxide.

12. The microcontroller of claim 11 further comprising means for selectively discharging said sense gate.