Digital down converter and method

• US 5,493,581 A
• Filed: 08/14/1992
• Issued: 02/20/1996
• Est. Priority Date: 08/14/1992
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Chester, David B., Young, William R.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): GHEBRETINSAE, TEMESGHEN
• Application Number:
  US07/930,170
• Time in Patent Office: 1,285 Days
• Field of Search: 375/97, 375/103, 375/81, 375/94, 375/98, 455/234.1, 455/239.1, 455/240.1, 455/250.1, 455/307, 329/304, 329/306, 329/307, 329/308, 364/724.1
• US Class Current: 375/350
• CPC Class Codes: H03D 7/165 at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002
• CPC Class Codes: H03H 17/06 Non-recursive filters
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/0021 Decimation, i.e. data rate reduction techniques H04B1/0025 takes precedence
• CPC Class Codes: H04B 1/26 for superheterodyne receivers multiple frequency-changing H03D7/16
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22
• CPC Class Codes: H04J 1/05 using digital techniques
• CPC Class Codes: H04Q 11/04 for time-division multiplexing H04Q11/0001 takes precedence

Abstract

A digital down converter for extracting a signal from a complex digital signal wherein the real and imaginary components of the complex digital signal are each modulated to shift the center frequency of the desired signal to zero frequency, decimated digitally to limit the bandwidth of each to the bandwidth of the desired signal and filtered to alter the shape thereof. The digital down converter includes a formatter for arranging the output of the desired signal in one of multiple output formats and a controller for programmably controlling the modulation, decimation and filtering and for selecting the desired output format.

Claims

1. A digital down converter, comprising:

(a) a data input;

(b) sine and cosine multipliers, each with a multiplicand input coupled to said data input;

(c) a sin/cos generator with sine output coupled to a multiplier input of said sine multiplier and with cosine output coupled to a multiplier input of said cosine multiplier;

(d) a phase generator with output coupled to a phase input of said sin/cos generator;

(e) a lowpass filter with first and second filter inputs coupled to product outputs of said sine and cosine multipliers, respectively;

(f) an output formatter with first and second format inputs coupled to first and second filter outputs of said lowpass filter, respectively;

(g) control logic coupled to said phase generator, said lowpass filter, and said formatter, wherein control words held in said control logic determine (i) the phase output of said phase generator and (ii) the output format of said formatter, said control words including ones which effectively couple said data input directly to said lowpass filter.

2. The converter of claim 1, wherein:

said control logic includes a serial port for inputting control words.

3. The converter of claim 1, wherein:

said lowpass filter includes a decimation filter with adjustable decimation rate followed by a fixed coefficient filter, wherein said decimation rate is determined by control words in said control logic.

4. The converter of claim 3, wherein:

said lowpass filter also includes a multiplier between said said decimation filter and said fixed coefficient filter, said multiplier compensating for the gain of said decimation filter.

5. The converter of claim 4, wherein:

said decimation filter includes an integrator stage followed by a sampling rate decimater followed by a comb stage.

6. The converter of claim 5, wherein:

said fixed coefficient filter includes a memory storing filter coefficients, a memory temporarily storing the outputs of said comb stage, and arithmetic circuitry for computing sums and products of said filter coefficients with said outputs of said comb stage, wherein said arithmetic circuitry computes said sums and products serially.

7. A method of extracting a desired signal of specified bandwidth from a digital signal comprising the steps of:

(a) providing a complex digital input signal having a real component and an imaginary component, each of said components comprised of a series of discrete time samples;

(b) individually modulating said real and imaginary components such that the center frequency of one sideband of said desired signal is down converted to zero frequency;

(c) decimating said real and imaginary components to thereby limit the bandwidth of each to the bandwidth of said desired signal;

(d) formatting said real and imaginary components according to one of multiple output formats;

(e) programmably controlling the modulation and decimation of said real and imaginary components and the bandwidth of said desired signal.

8. The method of claim 7 wherein said modulating step further comprises the steps of:

(a) generating a first modulation signal and a second modulation signal out-of-phase with said first modulation signal;

(b) selectively altering the phase of said first and second modulation signal; and

(c) multiplying said real component by said first modulation signal and said imaginary component by said second modulation signal.

9. The method of claim 8 wherein said first and second modulation signals are sine and cosine waves.

10. The method of claim 7 wherein said decimating step further comprises the steps of:

(a) sampling each component to thereby produce a sampled real component and a sampled imaginary component;

(b) scaling said sampled real component and said sampled imaginary component to thereby produce a real decimated output and an imaginary decimated output.

11. The method of claim 7 wherein said controlling step includes programmably controlling a phase increment between two modulation signals, a decimation rate, a scaling factor, the bandwidth of said desired signal, and the output format selected from said multiple output formats.

12. The method of claim 11 wherein said multiple output formats include two'"'"'s complement format, unsigned format, signed magnitude format and IEEE single precision floating point format.

13. A digital down converter which extracts a desired signal of specified bandwidth from a complex digital signal having an original sample rate comprising:

a modulator section for individually down converting the real and imaginary components of said complex digital signal such that the center frequency of said desired signal is zero frequency;

a filter section for limiting the bandwidth of said real and imaginary components by decimating the sample rate of each to thereby produce a real desired signal component and an imaginary desired signal component, each with a sample rate less than said original sample rate;

formatter means for arranging said real desired signal component and said imaginary desired signal component in one of multiple serial output formats; and

control means for programmably controlling said modulator section, said filter section and said formatter means.

14. The digital down converter of claim 13 wherein said modulator section further comprises:

a sin/cosine generator for producing at least two out-of-phase modulation signals;

a phase generator for producing a phase increment represented by a digital word which is sent to said sine/cosine generator for altering the phase of said modulation signals;

plural multipliers for modulating said real and imaginary components by multiplying said real component by one of said modulation signals and multiplying said imaginary component by another of said modulation signals;

15. The digital down converter of claim 13 wherein said filter section further comprises:

a decimating means having a specified decimation rate for decreasing the sample rate of said real and imaginary components and thereby producing a real desired signal component and an imaginary desired signal component;

a scaling means for changing the magnitude of said real desired signal component and said imaginary desired signal component by a factor corresponding to said specified decimation rate;

16. The digital down converter of claim 13 wherein said control means programmably controls a sine/cosine generator, a phase increment generated by a phase generator, a decimation rate, a scaling factor and an output format selected from said multiple serial output formats.

17. The digital down converter of claim 16 wherein said multiple serial output formats of said formatter section include two'"'"'s complement format, unsigned format, signed magnitude format and IEEE single precision floating point format.

18. A digital down converter which extracts a desired signal of specified bandwidth from a complex digital signal having a real component, an imaginary component and an original sample rate comprising:

a sin/cosine generator for producing at least two out-of-phase modulation signals;

a phase generator for producing a phase increment represented by a digital word which is sent to said sine/cosine generator for altering the phase of said modulation signals;

plural multipliers for modulating said real and imaginary components by multiplying said real component by one of said modulation signals and multiplying said imaginary component by another of said modulation signals to thereby down convert said real and said imaginary components such that the center frequency of said desired signal is zero frequency;

a decimation section having a specified decimation rate for decreasing the sample rate of said real and imaginary components and thereby producing a sampled real component and a sampled imaginary component with a sample rate less than said original sample rate;

a scaling section for changing the magnitude of said sampled real component and said imaginary component by a factor corresponding to said specified decimation rate;

a formatter section for arranging said sampled real component and said sampled imaginary component in one of multiple serial output formats; and

control means for programmably controlling said sine/cosine generator, said phase generator, said decimation section, said scaling section and said formatter section.