Image generator architecture employing tri-level fixed interleave processing and distribution buses

• US 5,493,643 A
• Filed: 05/03/1994
• Issued: 02/20/1996
• Est. Priority Date: 05/03/1994
• Status: Expired due to Term

• Current Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Original Assignee: Loral Aerospace Corp. (MHR Holdings LLC (New York))
• Inventors: Pheil, Douglas, Heinen, Mark N., Kenworthy, Mark L., Miller, Dale D., Cauble, Kent, Soderberg, Brian T.
• Primary Examiner(s): Powell, Mark R.
• Assistant Examiner(s): CHAUHAN, ULKA J
• Application Number:
  US08/237,286
• Time in Patent Office: 658 Days
• Field of Search: 395/162, 395/163, 395/164, 395/200, 395/250, 395/375, 395/425, 395/800, 364/228.3, 364/229.2, 364/240.1, 364/240.2, 364/578, 364/933.8
• US Class Current: 345/505
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G09B 9/003 for military purposes and tactics
• CPC Class Codes: G09B 9/301 by computer-processed or -generated image

Abstract

An image generator architecture in which tri-level fixed interleave processing provides medium grain parallelism for polygon, tiling, and pixel operations. Input data at each stage are divided into spatially distributed subsets that are interleaved among parallel processors using a fixed, precalculated mapping that minimizes correlation of local scene complexity with any one processor. The present tri-level fixed interleave processing architecture divides a processing task into a pseudo-random, fixed interleaved pattern of regions that are assigned to different processors. Each processor processes many of these randomly located regions. The assignment of processors to regions is a fixed repeating pattern. The highest level of fixed interleave processing is the allocation of fixed-size database regions (area modules) to polygon processors. The next level relates to image sub-region fixed interleave processing. At this level, the displayed image is divided into small sub-regions that are assigned to tilers in a pseudo-random, but fixed manner. This levels the load across all pixel processors. Typically, tilers process a large contiguous area of the image. The present invention uses small sub-regions (64×64 pixels) and assigns many sub-regions from different channels to a single tiler. Each tiler maintains equal loading .even with localized regions of high pixel processing. The third level relates to two-by-two pixel, fixed interleave processing. The image is further divided into 2×2 pixel blocks spread across multiple pixel operators on a tiler. This fine grain parallelism, in a fixed pseudo-random orientation, ensures equal loading across all pixel processors. The second aspect of the present invention is the use of polygon and pixel distribution buses. Maximum image generator configurability, expansion, and efficient processing is required for a variety of simulator configurations used in networked training environments. To accomplish this, distribution buses are implemented between all graphics processing stages.

Claims

1. An image generator architecture for generating a simulated image, said architecture comprising:

an image database;

a control bus;

a polygon distribution bus;

a pixel distribution bus;

an interface processor coupled to the control bus and to the image database for reading image data from the database;

a plurality of parallel polygon processors coupled to the control and polygon distribution busses for receiving data from the image database by way of the interface processor and coupled to the polygon distribution bus;

a plurality of texture filer pixel processors coupled between the polygon distribution bus and the pixel distribution bus that each comprise a tiler coupled to a plurality of parallel pixel processors; and

a plurality of parallel video processors coupled to the plurality of texture tiler pixel processors by way of the pixel distribution bus and coupled to the plurality of polygon processors and interface processor by way of the control bus.

2. The image generator architecture of claim 1 wherein each polygon processor processes one region of a plurality pseudo-random, fixed interleaved pattern of randomly located regions of the image that have a fixed repeating pattern to minimize correlation of local scene complexity with any one processor.

3. The image generator architecture of claim 1 wherein each tiler processes pseudo-random fixed interleaved sub-regions of the image to level the processing load across all pixel processors coupled thereto.

4. The image generator architecture of claim 1 wherein the plurality of parallel pixel processors each pseudo-randomly process two-by-two pixel blocks of the image to provide for equal loading across all pixel processors.