Polygon span interpolator with main memory Z buffer

• US 5,493,644 A
• Filed: 07/11/1991
• Issued: 02/20/1996
• Est. Priority Date: 07/11/1991
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Company (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Dowdell, Charles R., Sigal, Leon, Thayer, Larry J.
• Primary Examiner(s): Bayerl, Raymond J.
• Assistant Examiner(s): Tung, Kee M.
• Application Number:
  US07/728,423
• Time in Patent Office: 1,685 Days
• Field of Search: 395/162-166, 395/119-122, 395/133-143, 345/185
• US Class Current: 345/531
• CPC Class Codes: G06F 17/17 Function evaluation by approximation methods, e.g. inter- or extrapolation, smoothing, least mean square method G06F17/18 takes precedence ; interpolation for numerical control G05B19/18
• CPC Class Codes: G06T 15/80 Shading

Abstract

A scan converter incorporating a polygon span interpolator with main memory Z buffering. The span interpolator is initiated by instructions from a central processing unit (CPU), and when initiated, the span interpolator inerpolates input color and Z values in parallel. The span interpolator has its own state machine and can, once initiated, operate independent of the clock states of the CPU so that the CPU may process other data. Also, rather than using a dedicated memory as the Z buffer, the Z buffer shares main memory with the CPU. This allows the CPU to send pretranslated initial Z buffer addresses to the span interpolator when the span interpolator is initiated. Subsequent Z buffer addresses and color data addresses may be calculated in parallel with the input color and Z interpolations. Also, since the successive main memory and graphics addresses are known by the software, the memory controller of the invention allows data to be moved directly from main memory to the graphics address without CPU intervention and without having to pass the data through the data caches of the CPU. This greatly improves data transfer efficiencies since the cache penalties present in prior art software scan converters are not present.

Claims

1. A system for manipulating data for display on a display device, comprising:

a memory for storing data to be displayed;

a processing unit for processing said data at respective clock states thereof; and

memory controller means responsive to said processing unit for selectively accessing said data in said memory, said memory controller means including a free running processor whose processes are initiated by said processing unit but which processes predetermined coordinate data from said processing unit independent of the clock states of the processing unit and stores said processed predetermined coordinate data in a predetermined portion of said memory.

2. A system as in claim 1, further comprising a frame buffer connected to an output of said memory controller means, wherein said free running processor comprises means for interpolating said predetermined coordinate data and input color data for each pixel to be displayed and means for calculating, in parallel with interpolation by said interpolating means, addresses for storage of said interpolated predetermined coordinate data in said predetermined portion of said memory and of said input color data in said frame buffer.

3. A system as in claim 1, further comprising a frame buffer connected to an output of said memory controller means, wherein said memory controller means further comprises means for transferring data stored in said memory to said frame buffer without passing said data through said processing unit.

4. A computer graphics workstation for manipulating graphics data for display on a graphics display device, comprising:

main memory means for storing said graphics data;

a processing unit for processing said graphics data at respective clock states thereof; and

memory controller means responsive to said processing unit for selectively accessing said graphics data in said main memory means, said memory controller means including a free running span processor whose processes are initiated by said processing unit but which processes predetermined coordinate data independent of the clock states of the processing unit and stores said processed predetermined coordinate data in a predetermined portion of said main memory means.

5. A workstation as in claim 4, further comprising a frame buffer connected to an output of said memory controller means, wherein said free running span processor comprises means for interpolating said predetermined coordinate data and input color data for each pixel to be displayed and means for calculating, in parallel with interpolation by said interpolating means, addresses for storage of said interpolated portion of said memory means and of said input color data in said frame buffer.

6. A workstation as in claim 4, further comprising a frame buffer connected to an output of said memory controller means, wherein said memory controller means comprises means for transferring graphics data stored in said main memory means to said frame buffer without passing said graphics data through said processing unit.

7. A workstation as in claim 4, further comprising a data cache operatively connected to said main memory means for storing data.

8. A workstation as in claim 7, wherein said processing unit includes means for flushing data in said data cache to said main memory means prior to a memory access by said memory controller means when desired data is in the data cache, means for providing physical addresses to data to be accessed in said main memory means by said memory controller means and means for initiating interpolation by said free running span processor of respective data points on a span of said processed graphics data.

9. A workstation as in claim 4, wherein said predetermined coordinate data comprises Z coordinate data corresponding to a Z direction perpendicular to a display screen of said graphics display device and said predetermined portion of said main memory means comprises a Z buffer for storing old Z values, said memory controller means further comprising means for comparing said old Z values to processed Z values from said free running span processor.

10. A computer graphics workstation for manipulating graphics data for display on a graphics display device, comprising:

main memory means for storing said graphics data;

a processing unit for processing said graphics data at respective clock states thereof;

a graphics sub-system for outputting said processed graphics data for display on said graphics display device; and

memory controller means responsive to said processing unit for selectively accessing said graphics data in said main memory means, said memory controller means including a free running span processor whose processes are initiated by said processing unit but which processes coordinate data in a predetermined coordinate direction independent of said clock states of said processing unit and stores said processed coordinate data in a predetermined portion of said main memory means, said memory controller means further comprising means for transferring graphics data stored in said main memory means to and from said graphics sub-system without passing said graphics data through said processing unit.

11. A computer graphics workstation as in claim 10, wherein said graphics sub-system comprises a frame buffer.

12. A computer graphics workstation as in claim 10, wherein said graphics sub-system comprises a graphics accelerator system.

13. A method of manipulating data for display on a display device, comprising the steps of:

storing input data in a main memory;

geometrically transforming said input data in response to respective clock states of a processing unit;

initiating scan conversion of said geometrically transformed input data in a free running span processor in response to an instruction from said processing unit;

selectively accessing said data in said main memory with said free running span processor independent of the clock states of the processing unit;

comparing accessed Z coordinate data with input Z coordinate data from said processing unit;

outputting for display on said display device one of said accessed Z coordinate data and said input Z coordinate data as a result of the comparison in said comparing step; and

updating the accessed Z coordinate data in a predetermined portion of said main memory in accordance with the comparison in said comparing step.

14. A method as in claim 13, comprising the further steps of interpolating said input Z coordinate data and input color data for each pixel to be displayed and, in parallel with said interpolating step, calculating addresses for storage of said interpolated input Z coordinate data in said predetermined portion of said main memory and of said interpolated input color data in a frame buffer.

15. A method as in claim 14, comprising the further step of transferring data stored in said main memory to said frame buffer without passing said data through said processing unit.

16. A method as in claim 13, wherein said scan conversion initiating step comprises the steps of flushing data in a data cache memory of said main memory to said main memory prior to access in said selectively accessing step, providing physical addresses to data to be accessed in said main memory during said selectively accessing step and initiating a span interpolation by said free running span processor of respective data points on a span of said geometrically transformed input data.

17. A method as in claim 16, comprising the further steps of calculating, in parallel with said interpolating and address calculating steps, a number of pixels within a span to be displayed as a span count and discontinuing the interpolation for the present scan line when the span count has been reached.