Fast AGC for TDMA radio systems

• US 5,493,712 A
• Filed: 03/23/1994
• Issued: 02/20/1996
• Est. Priority Date: 03/23/1994
• Status: Expired due to Term

• Current Assignee: AT&T IPM Corp. (AT&T, Inc.)
• Original Assignee: AT&T Corporation (AT&T, Inc.)
• Inventors: Sreenath, Krishnamurthy, Ramesh, Nallepilli S.
• Primary Examiner(s): Urban, Edward F.
• Assistant Examiner(s): LE, THANH C
• Application Number:
  US08/216,371
• Time in Patent Office: 699 Days
• Field of Search: 455/234.1, 455/234.2, 455/235.1, 455/241.1, 455/244.1, 455/245.1, 455/245.2, 455/249.1, 455/251.1, 455/239.1, 455/250.1, 455/242.2, 330/136, 330/129, 330/184, 307/493, 375/345, 327/306, 327/331, 327/334, 327/350
• US Class Current: 455/234.2
• CPC Class Codes: H03G 3/3047 for intermittent signals, e.g. burst signals

Abstract

Disclosed is a circuit for automatic gain control (AGC) of random access channels (RACH) and traffic channels in a radio system. The amplitude of the input signal is detected at an intermediate frequency (IF) stage, digitized, and coupled to a digital signal processor (DSP) which produces an AGC signal for reducing the gain of the input when the input crosses a threshold value. For RACH bursts, the AGC signal tracks the input signal when it crosses the threshold and the AGC signal remains at a constant value for the the remainder of the time slot unless and until the input increases a threshold amount over its previous highest value. For traffic channels, the DSP will use the AGC signal from the RACH burst as an initial value and change the AGC signal only if the detected input is outside a predetermined range.

Claims

1. A circuit for providing automatic gain control in a radiotelephone system which receives signals in a succession of time slots which system includes at least one random access time slot in a broadcast frame also including traffic time slots, the circuit comprising:

means for receiving an intermediate frequency input signal in the access time slot;

means for detecting the amplitude of the input signal;

means for converting the amplitude of the detected signal to a digital representative;

means coupled to the converting means for providing an automatic gain control signal in said access time slot which is proportional to the amplitude of the detected signal only after the said amplitude exceeds a first threshold level and which is kept at a first constant value until the end of the access time slot unless the said amplitude exceeds a second threshold level which is greater than the first threshold level and, in that event, the gain control signal is held at a second constant value greater than the first constant value until the end of the access time slot;

means for coupling the automatic gain control signal to at least one attenuator in the path of the immediate input frequency signal so as to adjust the gain of that signal in a feed forward loop;

means for comparing a second automatic gain control signal derived from an input signal from a subsequent traffic time slot with the automatic gain control signal value derived from the access time slot, and substituting the second automatic gain control signal in the event that the difference between the two automatic gain control signal values falls outside a predetermined range.

2. The circuit according to claim 1 wherein the means for detecting the amplitude comprises a logarithmic amplifier which produces an output signal proportional to the log of the amplitude of the input signal.

3. The circuit according to claim 2 wherein the logarithmic amplifier comprises a receiver circuit, a crystal oscillator, and a filter.

4. The circuit according to claim 1 wherein the means for providing an automatic gain control signal comprises a digital signal processor.

5. The circuit according to claim 4 wherein the DSP triggers a window timer in the event the first or second threshold level is exceeded, during which time the gain control signal is increased proportionally to the input signal, the timer being set for a time corresponding to the rise time of the input signal.

6. The circuit according to claim 1 wherein the second threshold level is set to at least twice the first threshold level.

7. The circuit according to claim 1 wherein the means for comparing is coupled to a microprocessor in order to determine if the input signal is from an access time slot or a traffic time slot.