Method of manufacturing electronic component and measuring characteristics of same

• US 5,493,769 A
• Filed: 08/02/1994
• Issued: 02/27/1996
• Est. Priority Date: 08/05/1993
• Status: Expired due to Term

• Current Assignee: Murata Manufacturing Co Limited
• Original Assignee: Murata Manufacturing Co Limited
• Inventors: Sakai, Norio, Kubota, Kenji
• Primary Examiner(s): Hall, Carl E.
• Application Number:
  US08/284,150
• Time in Patent Office: 574 Days
• Field of Search: 29/25.42, 29/25.35, 29/854-856, 29/852, 29/853, 29/593, 29/602.1
• US Class Current: 29/593
• CPC Class Codes: H01C 1/14 Terminals or tapping points or electrodes specially adapted for resistors in general H01R; Arrangements of terminals or tapping points or electrodes on resistors
• CPC Class Codes: H01G 4/232 electrically connecting two or more layers of a stacked or rolled capacitor
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 2201/09036 Recesses or grooves in insulating substrate recess in metallic substrate H05K2201/09745
• CPC Class Codes: H05K 2201/0909 Preformed cutting or breaking line
• CPC Class Codes: H05K 2201/0919 Exposing inner circuit layers or metal planes at the side edge of the PCB or at the walls of large holes shielding provided by an inner layer of PCB H05K2201/0723
• CPC Class Codes: H05K 3/0052 Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
• CPC Class Codes: H05K 3/403 Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof H05K3/4092 takes precedence
• CPC Class Codes: Y10T 29/435 Solid dielectric type
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor
• CPC Class Codes: Y10T 29/49169 Assembling electrical component directly to terminal or elongated conductor

Abstract

A method of manufacturing a multilayer electronic component having one major surface which can be completely used as a mounting surface for another electronic component to form a composite component includes the steps of forming a groove in the mother laminate along a cutting line, forming external electrodes on side surfaces of the groove and then dividing the mother laminate along the cutting line to divide the groove thereby forming a plurality of multilayer electronic components that are independent of each other. The method of forming the electronic components allows for measuring electrical characteristics of the individual multilayer electronic components while the components are still part of the mother laminate.

Claims

1. A method for manufacturing multilayer electronic components, comprising the steps of:

preparing a mother laminate, to be cut along at least one cutting line for obtaining a plurality of multilayer electronic components, said mother laminate being formed by stacking a plurality of mother insulating sheets having internal circuit elements located thereon for forming said multilayer electronic components, said internal circuit elements being located in respective regions formed when said mother laminate is divided along said at least one cutting line;

forming a groove in said mother laminate along said at least one cutting line to electrically isolate adjacent electronic components;

applying a plurality of external electrodes on at least one surface of said groove so that said plurality of external electrodes are electrically connected with said internal circuit elements; and

dividing said mother laminate along said at least one groove.

2. A method of manufacturing multilayer electronic components in accordance with claim 1, wherein said mother insulating sheets are ceramic green sheets, said method further comprising a step of firing said mother laminate.

3. A method of manufacturing multilayer electronic components in accordance with claim 1, further comprising a step of forming at least one notch in at least one of a bottom surface of said groove and a major surface of said mother laminate disposed opposite to said bottom surface so that said notch is located along said groove.

4. A method of manufacturing multilayer electronic components in accordance with claim 1, wherein said step of applying said external electrodes comprises a step of applying said external electrodes to both opposite side surfaces of said groove independently of each other.

5. A method of manufacturing multilayer electronic components in accordance with claim 1, wherein said step of applying said external electrodes comprises the steps of applying metal paste materials for defining said external electrodes to both opposite side surfaces of said groove so that said external electrodes are connected with each other, and dividing the metal paste materials for making said external electrodes independent of each other.

6. A method for measuring characteristics of multilayer electronic components, comprising the steps of:

preparing a mother laminate, to be cut along at least one cutting line for obtaining a plurality of multilayer electronic components, said mother laminate being formed by stacking a plurality of mother insulating sheets having internal circuit elements located thereon for forming said multilayer electronic components, said internal circuit elements being located in respective regions formed when said mother laminate is divided along said at least one cutting line;

forming a groove in said mother laminate along said at least one cutting line to electrically isolate adjacent electronic components;

applying a plurality of external electrodes on at least one surface of said groove to be electrically connected with said internal circuit elements; and

measuring electric characteristics of at least one of said multilayer electronic components via said external electrodes while said multilayer electronic components are part of said mother laminate.

7. A method for measuring characteristics of multilayer electronic components in accordance with claim 6, wherein said step of applying said plurality of external electrodes comprises a step of applying said plurality of external electrodes to both opposite side surfaces of said groove independently of each other.

8. A method of measuring characteristics of multilayer electronic components in accordance with claim 6, wherein said step of applying said plurality of external electrodes comprises the steps of applying metal paste materials for defining said external electrodes to both opposite side surface of said groove so that said plurality of electrodes connected with each other, and dividing said metal paste materials for making said plurality of external electrodes independently of each other.