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Variable delay circuit

  • US 5,495,197 A
  • Filed: 02/24/1995
  • Issued: 02/27/1996
  • Est. Priority Date: 08/14/1991
  • Status: Expired due to Fees
First Claim
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1. A fine variable delay circuit comprising:

  • a first exclusive-OR gate grounded at one input side and connected at another input side to a delay input terminal;

    a second exclusive-OR gate connected at one input side to a select signal input terminal and at another input side to said delay input terminal;

    a capacitor connected between an output side of said first exclusive-OR gate and an output side of said second exclusive-OR gate; and

    a buffer connected at an input side to the connection point of said capacitor and said output side of said first exclusive-OR gate and at an output side to a delay output terminal, said buffer outputting a logical level.

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