Variable delay circuit
First Claim
1. A fine variable delay circuit comprising:
- a first exclusive-OR gate grounded at one input side and connected at another input side to a delay input terminal;
a second exclusive-OR gate connected at one input side to a select signal input terminal and at another input side to said delay input terminal;
a capacitor connected between an output side of said first exclusive-OR gate and an output side of said second exclusive-OR gate; and
a buffer connected at an input side to the connection point of said capacitor and said output side of said first exclusive-OR gate and at an output side to a delay output terminal, said buffer outputting a logical level.
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Abstract
First and second exclusive-OR gates (hereinafter referred to as EXOR gates) are provided, which are both connected at one input side to a delay input terminal. The other input side of the first EXOR gate is grounded and the other input side of the second EXOR gate is connected to a select signal input terminal. A capacitor is connected between the output side of the first EXOR gate and the output side of the second EXOR gate. The output side of the first EXOR gate is connected to a delay output terminal by way of a buffer which outputs logical levels. The buffer has a threshold value and outputs one or the other binary logical level depending on whether the input thereto is above or below a threshold value.
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Citations
2 Claims
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1. A fine variable delay circuit comprising:
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a first exclusive-OR gate grounded at one input side and connected at another input side to a delay input terminal; a second exclusive-OR gate connected at one input side to a select signal input terminal and at another input side to said delay input terminal; a capacitor connected between an output side of said first exclusive-OR gate and an output side of said second exclusive-OR gate; and a buffer connected at an input side to the connection point of said capacitor and said output side of said first exclusive-OR gate and at an output side to a delay output terminal, said buffer outputting a logical level. - View Dependent Claims (2)
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Specification
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- Resources
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Current AssigneeAdvantest Corporation
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Original AssigneeAdvantest Corporation
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InventorsHayashi, Yokichi, Ochiai, Katsumi, Tsukahara, Hiroshi, Watanabe, Naoyoshi, Yamada, Masuhiro
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Primary Examiner(s)Callahan, Timothy P.
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Assistant Examiner(s)ZWEIZIG, JEFFERY SHAWN
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Application NumberUS08/394,249Time in Patent Office368 DaysField of Search326/52, 326/54, 326/55, 327/261, 327/263, 327/264, 327/266, 327/276, 327/278, 327/281, 327/283, 327/284, 327/285, 327/288, 327/290, 327/392-401US Class Current327/276CPC Class CodesH03K 17/163 Soft switchingH03K 5/131 Digitally controlledH03K 5/133 using a chain of active del...
