Master-slave data transmission system employing a flexible single-wire bus
First Claim
1. A data transmission system for transmitting and receiving data via a single wire bus, said system comprising:
- at least one master unit coupled to said single wire bus and operative to send data to or read data from at least one slave unit via an input/output stage wherein data transmission takes place via said single wire bus, said master unit including address generating means for providing an address of variable arbitrarily predetermined length to said slave unit, wherein said address concludes with a first label;
at least one slave unit coupled to said single wire bus, with each said slave unit having an arbitrarily predetermined length address and including an address length checking device responsive to said address sent from said master unit to determine selection of said slave unit, said address length checking device including shift register means for serially receiving and storing said address of variable arbitrarily predetermined length from said master unit, means for detecting said first label to initiate an address check; and
comparison means for checking whether said address sent from said master unit matches said address of said slave unit.
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Abstract
A master-slave data transmission system employs a flexible single-wire bus and where any master unit can send data to or read data from any slave at a single time. Data transfer is accomplished by means of a flexible message format having a variable-length address section and a variable-length data section, with the beginning and end of the individual message sections being defined by labels, and a fixed bit clock being transmitted for a given interval before and/or after the message. During multiple master operation, a priority control arrangement prevents two or more masters from accessing the single-wire bus at the same time.
68 Citations
20 Claims
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1. A data transmission system for transmitting and receiving data via a single wire bus, said system comprising:
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at least one master unit coupled to said single wire bus and operative to send data to or read data from at least one slave unit via an input/output stage wherein data transmission takes place via said single wire bus, said master unit including address generating means for providing an address of variable arbitrarily predetermined length to said slave unit, wherein said address concludes with a first label; at least one slave unit coupled to said single wire bus, with each said slave unit having an arbitrarily predetermined length address and including an address length checking device responsive to said address sent from said master unit to determine selection of said slave unit, said address length checking device including shift register means for serially receiving and storing said address of variable arbitrarily predetermined length from said master unit, means for detecting said first label to initiate an address check; and
comparison means for checking whether said address sent from said master unit matches said address of said slave unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. In a master-slave transmission system including at least one master unit operative to send data to or read data from at least one slave unit via an input/output stage, with a data transmission taking place via a single wire bus, said system providing a format for transmission and reception of messages via said bus, said format including:
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an address section defining at least a variable arbitrarily predetermined length address of a slave unit; a data portion including transmitted or read data; and a start and end information signal defining the start and end of said message format, the combination therewith including; at least one master unit connected to said single wire bus, said master unit having an address generating means for providing an address of a variable length which is arbitrarily predetermined from message to message and where the end of said address is determined by a first label; at least one slave unit connected to said single wire bus, with said slave unit being addressed by an arbitrarily predetermined length address and including an address length checking device responsive to said message to decode said address in order to determine selection of said slave unit; with said data portion of said transmitted message having a length of which is arbitrarily predeterminable from message to message; a bit clock generator located in said master unit for generating a clock which is transmitted before or after said message; means located in said master unit for providing logic states of bits in said message defined by a first or second temporal ratio between a first state and a second state of said single-wire bus, and to provide said first, second, and third labels with said bits of said end information signal defined by a third temporal ratio between said first and second states, including means responsive to said second temporal ratio wherein duration of a changed state is longer in said second temporal ratio than in said first temporal ratio, with the transition from said second state to said first defining the beginning of a respective bit clock period, with said master unit including detecting means responsive to said start of information signal to prevent any master units not generating a message to cease message generation while said message occupies said bus; and means in said master unit for inserting a synchronizing bit in said format after said first label; means in said slave unit responsive to said synchronizing bit to maintain said first logic state of said synchronizing bit to indicate to said master unit that processing of said message is to continue by said slave unit; means in said slave unit for providing a not-ready signal by changing said synchronizing bit to said second logic state to indicate to said master that said slave unit is not ready to process said message; means located in said master unit operative to detect said not-ready signal to enable said master unit to relinquish said bus by sending an end information signal; and an output error detector located in said master unit and operative to compare said temporal ratios present on said bus with said data generated from said master in order to detect an error to prevent contention between two or more master units during a transmission. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. In a master-slave transmission system including at least one master unit operative to send data to or read data from at least one slave unit via an input/output stage, with a data transmission taking place via a single wire bus, said system providing a format for transmission and reception of messages via said bus, said format including:
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an address section defining at least a variable arbitrarily predetermined length address of a slave unit; a data portion including transmitted or read data; and a start and end information signal defining the start and end of said message format, the combination therewith including; at least one master unit connected to said single wire bus, said master unit having an address generating means for providing an address of a variable length which is arbitrarily predetermined from message to message and where the end of said address is defined by a first label; at least one slave unit connected to said single wire bus, with said slave unit being addressed by an arbitrarily predetermined length address and including an address length checking device responsive to said message to decode said address in order to determine selection of said slave unit, with said data portion of said transmitted message having a length of which is arbitrarily predeterminable from message to message; means in said master unit for inserting a synchronizing bit in said format after said first label; means in said slave unit responsive to said synchronizing bit to maintain a first logic state of said synchronizing bit to indicate to said master unit that processing of said message is to continue by said slave unit; means in said slave unit for providing a not-ready signal by changing said synchronizing bit to a second logic state to indicate to said master that said slave unit is not ready to process said message; means located in said master unit operative to detect said not-ready signal to enable said master unit to relinquish said bus by sending an end information signal; and detecting means in said master unit responsive to said start of information signal to prevent any master units not generating said message to cease message generation while said message occupies said bus, and including an output error detector located in said master unit and operative to prevent contention between two or more master units during a transmission.
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Specification