Apparatus for concealing detected erroneous data in a digital image signal

• US 5,495,298 A
• Filed: 03/22/1994
• Issued: 02/27/1996
• Est. Priority Date: 03/24/1993
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Kondo, Tetsujiro, Uchida, Masashi, Nakaya, Hideo
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Cohen, Cheryl
• Application Number:
  US08/215,612
• Time in Patent Office: 707 Days
• Field of Search: 348/615, 348/616, 348/421, 358/314
• US Class Current: 348/615
• CPC Class Codes: H04N 19/895 in combination with error concealment
• CPC Class Codes: H04N 5/9261 involving data reduction
• CPC Class Codes: H04N 5/945 for signals recorded by pulse code modulation

Abstract

An apparatus for concealing error data of pixel data in a digital image signal. The apparatus includes a deframing circuit for detecting errors every predetermined unit to generate a first error flag in high order bit planes including at least the most significant bit plane of bit planes of pixel data in a received digital image signal and for forming a second error flag representing the presence or absence of an error in each of the bits forming the pixel data every pixel data in the high order bit planes on the basis of the first error flag. The apparatus further includes an error correcting device for calculating a plurality of possible data values of the pixel data and for selecting one data value from among the plurality of possible data values, taking the correlation between the pixel data and surrounding pixel data into consideration, on the basis of the second error flag representing the presence or absence of an error in each of the bits forming the pixel data when the pixel data has an error.

Claims

1. An apparatus for concealing error data of pixel data in a received digital image signal, comprising:

receiving means for receiving said digital image signal;

deframing means for detecting errors in said received digital image signal every predetermined unit, whereby each unit defines one of a plurality of bit planes, to generate a first error flag in high order bit planes including at least a most significant bit plane of bit planes having a plurality of bits, said first error flag representing a presence or absence of an error in each byte, and for forming a second error flag for said high order bit planes on the basis of said first error flag, said second error flag representing a presence or absence of an error in each bit plane; and

error correcting means for calculating a plurality of possible data values of said pixel data based upon said second error flag and for selecting one data value from among said plurality of possible data values by taking a correlation between each of said possible data values and surrounding pixel data when said second error flag represents the presence of an error in said pixel data.

2. The apparatus according to claim 1, wherein said digital image signal which is received by said receiving means is shuffled and is constructed by arranging each bit for each of a plurality of said bit planes comprising a plurality of said pixel data and wherein a plurality of bits of said pixel data form at least one unit of error detection in each of said bit planes each including a plurality of bits pixel data located at positions different from those obtained when the pixel data is deshuffled.

3. The apparatus according to claim 2, wherein said error correcting means selects one data value from among said plurality of data values which are calculated by taking the correlation between each of said possible data values and two pixel data horizontally adjacent thereto.

4. An apparatus for concealing error data in a digital image data signal, said apparatus comprising:

means for receiving units of data corresponding to said digital image data signal in which each of said units includes a plurality of data bits;

deframing means for detecting errors in the received units of data and for generating a flag identifying whether the bits of each respective unit contain an error; and

error correcting means for calculating a plurality of data values for the respective unit having a detected error based upon the respective flag, and for selecting one of the calculated data values from the plurality of calculated data values by considering correlation between each of said calculated data values and data adjacent thereto.

5. The apparatus according to claim 4, wherein said flag has a plurality of bits.

6. The apparatus according to claim 4, wherein said flag has a number of bits equal to the number of bits in each of said units.

7. The apparatus according to claim 6, wherein each of said units has four data bits and wherein said flag has four bits.

8. An apparatus for concealing error data in a digital image data signal, said apparatus comprising:

means for receiving units of data corresponding to said digital image data signal in which each of said units includes dynamic range data, minimum value data and a number of quantized data each having a plurality of data bits;

deframing means for detecting errors in the received units of data, said deframing means generates a first flag upon the detection of an error in said dynamic range data and said minimum value data and generates a second flag which identifies whether the data bits of a respective quantized data contain an error; and

error correcting means for calculating a plurality of data values for the respective quantized data having a detected error based upon the respective second flag, and for selecting one of the calculated data values from the plurality of calculated data values by considering correlation between each of said calculated data values and data adjacent thereto.

9. The apparatus according to claim 8, wherein said second flag has a number of bits equal to the number of bits in each said quantized data.

10. The apparatus according to claim 9, wherein said first flag has one bit.

11. The apparatus according to claim 9, wherein each said quantized data has four data bits and wherein said second flag has four bits.