Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processing

• US 5,495,419 A
• Filed: 04/19/1994
• Issued: 02/27/1996
• Est. Priority Date: 04/19/1994
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Scepanovic, Ranko, Koford, James S., Boyle, Douglas B., Rostoker, Michael D., Jones, Edwin R.
• Primary Examiner(s): Trammell, James P.
• Application Number:
  US08/229,826
• Time in Patent Office: 679 Days
• Field of Search: 364/468, 364/488-493, 395/10, 395/13
• US Class Current: 700/121
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.

Claims

1. A physical design automation system for producing an optimized cell placement for an integrated circuit chip, comprising:

a decomposer for decomposing a placement optimization methodology into a plurality of cell placement optimization processes;

a plurality of parallel processors for performing said optimization processes simultaneously on input data representing said chip;

a recomposer for recomposing results of said optimization processes and producing an optimized cell placement corresponding thereto; and

a controller for analyzing a fitness of said optimized cell placement and controlling the parallel processors to selectively repeat performing said optimization processes for further optimizing said optimized cell placement if said fitness does not satisfy a predetermined criterion;

in which the controller identifies low fitness areas of said optimized placement and selectively assigns the processors to repeat performing said optimization processes on said low fitness areas respectively.

2. A system as in claim 1, in which the controller controls the processors individually.

3. A system as in claim 1, in which said optimization processes comprise genetic alteration.

4. A system as in claim 1, in which said optimization processes comprise simulated annealing.

5. A system as in claim 1, in which the controller defines a plurality of movable windows that delineate subsets of cells in said low fitness areas respectively, and assigns the processors to repeat performing said optimization processes on said subsets delineated by said windows respectively.

6. A system as in claim 1, in which:

the controller identifies cells in said low fitness areas having high interconnect congestion and assigns said cells to the parallel processors respectively; and

the parallel processors compute centroids as a first predetermined function of locations of cells to which said cells are connected;

compute first distances from current locations of said cells to said centroids;

compute second distances as second predetermined functions of said first distances; and

move said cells from said current locations toward said centroids by said second distances respectively.

7. A system as in claim 1, in which:

the process decomposer generates a plurality of initial placements;

the parallel processors perform said cell optimization processes on said initial placements to produce a plurality of processed cell placements respectively; and

the process recomposer designates a processed cell placement having a highest fitness as said optimized cell placement.

8. A system as in claim 1, in which the process decomposer generates an initial placement, divides said initial placement into a plurality of areas and assigns the processors to perform said optimization processes on said areas respectively.

9. A system as in claim 1, in which the process decomposer generates an initial placement, divides said initial placement into a plurality of contiguous areas and assigns the processors to perform said optimization processes on said areas respectively.

10. A system as in claim 1, in which the process decomposer generates a plurality of different initial placements and assigns the processors to perform said optimization processes on said initial placements respectively.

11. A system as in claim 1, in which the parallel processors comprise:

a plurality of worker processors for independently performing said optimization processes and producing results; and

a host processor for distributively assigning said optimization processes to the worker processors in response to work requests received therefrom;

each worker processor sending a work request to the host processor after completing an optimization process.

12. A physical design automation system for producing an optimized cell placement for an integrated circuit chip, comprising:

a decomposer for decomposing a placement optimization methodology into a plurality of cell placement optimization processes;

a plurality of parallel processors for performing said optimization processes simultaneously on input data representing said chip;

a recomposer for recomposing results of said optimization processes and producing an optimized cell placement corresponding thereto; and

a controller for analyzing a fitness of said optimized cell placement and controlling the parallel processors to selectively repeat performing said optimization processes for further optimizing said optimized cell placement if said fitness does not satisfy a predetermined criterion, in which;

the process decomposer generates a plurality of initial placements;

the parallel processors perform said cell optimization processes on said initial placements to produce a plurality of processed cell placements respectively;

the process recomposer designates a processed cell placement having a highest fitness as said optimized cell placement; and

said optimization processes comprise genetic crossover between said initial placements.

13. A physical design automation system for producing an optimized cell placement for an integrated circuit chip, comprising:

a decomposer for decomposing a placement optimization methodology into a plurality of cell placement optimization processes;

a plurality of parallel processors for performing said optimization processes simultaneously on input data representing said chip;

a recomposer for recomposing results of said optimization processes and producing an optimized cell placement corresponding thereto; and

a controller for analyzing a fitness of said optimized cell placement and controlling the parallel processors to selectively repeat performing said optimization processes for further optimizing said optimized cell placement if said fitness does not satisfy a predetermined criterion, in which;

said optimization processes comprise different algorithms respectively;

the processor generates an initial placement;

the parallel processors perform said cell optimization processes on said initial placement to produce a plurality of processed cell placements respectively; and

the process recomposer designates a processed cell placement having highest fitness as said optimized cell placement.

14. A physical design automation system for producing an optimized cell placement for an integrated circuit chip, comprising:

a decomposer for decomposing a placement optimization methodology into a plurality of cell placement optimization processes;

a plurality of parallel processors for performing said optimization processes simultaneously on input data representing said chip;

a recomposer for recomposing results of said optimization processes and producing an optimized cell placement corresponding thereto; and

a controller for analyzing a fitness of said optimized cell placement and controlling the parallel processors to selectively repeat performing said optimization processes for further optimizing said optimized cell placement if said fitness does not satisfy a predetermined criterion;

in which the process decomposer generates an initial placement, divides cells of said initial placement into a plurality of nets of interconnected cells and assigns the processors to perform said optimization processes on said nets respectively.

15. A system as in claim 14, in which said optimization processes comprise cell interconnect routing.

16. A physical design automation system for producing an optimized cell placement for an integrated circuit chip, comprising:

a decomposer for decomposing a placement optimization methodology into a plurality of cell placement optimization processes;

a plurality of parallel processors for performing said optimization processes simultaneously on input data representing said chip;

a recomposer for recomposing results of said optimization processes and producing an optimized cell placement corresponding thereto; and

a controller for analyzing a fitness of said optimized cell placement and controlling the parallel processors to selectively repeat performing said optimization processes for further optimizing said optimized cell placement if said fitness does not satisfy a predetermined criterion;

in which the process decomposer generates an initial placement, divides cells of said initial placement into a plurality of groups of cells in accordance with a predetermined hierarchial organization and assigns the processors to perform said optimization processes on said groups respectively.

17. A system as in claim 16, in which said optimization processes comprise cell interconnect routing.