Low power voltage detector circuit including a flash memory cell

• US 5,495,453 A
• Filed: 10/19/1994
• Issued: 02/27/1996
• Est. Priority Date: 10/19/1994
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Intel Corporation
• Inventors: Wojciechowski, Kenneth E., Taub, Mase J.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): MAI, SON LUU
• Application Number:
  US08/326,689
• Time in Patent Office: 496 Days
• Field of Search: 365/189.09, 365/226, 365/227, 365/185, 365/228, 365/229
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence

Abstract

A voltage detector circuit for detecting when an input voltage exceeds a trip-point voltage. The voltage detector circuit includes a nonvolatile memory cell having a select gate coupled to the input voltage, a drain coupled to a first node, a source coupled to system ground, and a floating gate. The nonvolatile memory cell is used primarily as a pull-down transistor, and the threshold voltage of nonvolatile memory is programmed to be the trip-point voltage such that the first node is set to system ground if the input voltage exceeds the trip-point voltage. The voltage detector circuit also includes a first transistor having a control electrode coupled to a biasing voltage, a first terminal coupled to the first node, and a second terminal coupled to a supply voltage. The control electrode is operative to couple the first terminal to the second terminal in response to the biasing voltage. The first transistor sets the first node to the input voltage if the input voltage is less than the trip-point voltage. The voltage detector further includes an output circuit coupled to the first node. The output circuit is operative to indicate whether the input voltage exceeds the trip-point voltage in response to the voltage of the first node.

Claims

1. A voltage detector circuit for detecting when an input voltage exceeds a trip-point voltage, comprising:

a nonvolatile memory cell including a select gate coupled to the input voltage, a drain coupled to a first node, a source coupled to a first voltage, and a floating gate, wherein the nonvolatile memory cell has a programmable threshold voltage and the threshold voltage is programmed such that the nonvolatile memory cell is switched on to set the first node to the first voltage if the input voltage exceeds the trip-point voltage; and

a first transistor including a control electrode coupled to a biasing voltage, a first terminal coupled to the first node, and a second terminal coupled to the input voltage, the control electrode for coupling the first terminal to the second terminal in response to the biasing voltage, wherein the first transistor sets the first node to the input voltage if the input voltage is less than the trip-point voltage; and

an output circuit coupled to the first node, the output circuit being operative to indicate whether the input voltage exceeds the trip-point voltage in response to the voltage of the first node.

2. The voltage detector circuit of claim 1, wherein the output circuit comprises an inverter having an input coupled to the first node.

3. The voltage detector circuit of claim 2, wherein the inverter is powered by the input voltage.

4. The voltage detector circuit of claim 2, wherein an output of the inverter is coupled to the gate of the first transistor such that the first transistor is switched off when the voltage of the first node is at the first voltage.

5. The voltage detector circuit of claim 2, wherein the nonvolatile memory cell is a flash electrically erasable programmable read only memory.

6. The voltage detector circuit of claim 5, further comprising a second transistor coupled between the nonvolatile memory cell and the first node such that a first terminal of the second transistor is coupled to the drain of nonvolatile memory cell and a second terminal of the second transistor is coupled to the first node, wherein a voltage is applied to a control electrode of the second transistor such that a voltage at the drain of the nonvolatile memory cell is limited to a predetermined maximum value.

7. The voltage detector circuit of claim 6, further comprising

a third transistor coupled between the supply voltage and the first transistor such that a first terminal of the third transistor is coupled to the second terminal of the first transistor and a second terminal of the third transistor is coupled to the supply voltage;

and

a feedback control circuit coupled to an output of the inverter and the control electrode of the third transistor, the feedback control circuit being operative to supply the output of the inverter to the control electrode of the third transistor when the voltage detector is operating in a first mode and being operative to supply a constant voltage to the control electrode of the third transistor such that the third transistor is switched on when the voltage detector circuit is operating in a second mode.

8. A nonvolatile memory device comprising:

a conductor for coupling to receive an input voltage;

a memory cell array comprising a plurality of nonvolatile memory cells arranged in a matrix of rows and columns, wherein the memory cell array is coupled to receive the input voltage;

a voltage detector circuit coupled to the conductor for detecting whether the input voltage exceeds a trip-point voltage, the voltage detector circuit comprising;

a nonvolatile memory cell including a select gate coupled to the input voltage, a drain coupled to a first node, a source coupled to system ground, and a floating gate, wherein the nonvolatile memory cell has a programmable threshold voltage and the threshold voltage is programmed such that the nonvolatile memory cell is switched on to set the first node to system ground if the input voltage exceeds the trip-point voltage;

a first transistor including a control electrode coupled to a biasing voltage, a first terminal coupled to the first node, and a second terminal coupled to the input voltage, the control electrode for coupling the first terminal to the second terminal in response to the biasing voltage;

an inverter having an input coupled to the first node and an output for indicating whether the input voltage exceeds the trip-point voltage; and

a control circuit coupled to the output of the inverter and the control electrode of the first transistor, the control circuit for supplying the output of the inverter to the control electrode of the first transistor as the biasing voltage when power is first applied to the nonvolatile memory device such that the first transistor is switched off when the output of the inverter indicates that the input voltage exceeds the trip-point voltage, and for supplying the biasing voltage to the control electrode of the first transistor when erase and program operations are performed on the memory cell array such that the first transistor is switched on continuously.

9. A nonvolatile memory device comprising:

a conductor for coupling to receive an input voltage;

a memory cell array comprising a plurality of nonvolatile memory cells arranged in a matrix of rows and columns, wherein the memory cell array is coupled to receive the input voltage;

a voltage detector circuit coupled to the conductor for detecting whether the input voltage exceeds a trip-point voltage, the voltage detector circuit comprising;

a nonvolatile memory cell including a select gate coupled to the input voltage, a drain coupled to a first node, a source coupled to system ground, and a floating gate, wherein the nonvolatile memory cell has a programmable threshold voltage and the threshold voltage is programmed such that the nonvolatile memory cell is switched on to set the first node to system ground if the input voltage exceeds the trip-point voltage;

an inverter having an input coupled to the first node and an output, the inverter for indicating that the input voltage is less than the trip-point voltage by setting the output to system ground and for indicating that the input voltage is at least the trip-point voltage by setting the output to the input voltage; and

a first transistor including a control electrode coupled to a biasing voltage, a first terminal coupled to the first node, and a second terminal coupled to the input voltage, the control electrode for coupling the first terminal to the second terminal in response to the biasing voltage, wherein the first transistor sets the first node to the input voltage if the input voltage is less than the trip-point voltage.

10. A nonvolatile memory device comprising:

a conductor for coupling to receive an input voltage;

a memory cell array comprising a plurality of nonvolatile memory cells arranged in a matrix of rows and columns, wherein the memory cell array is coupled to receive the input voltage;

a voltage detector circuit coupled to the conductor for detecting whether the input voltage exceeds a trip-point voltage, the voltage detector circuit comprising;

a nonvolatile memory cell including a select gate coupled to the input voltage, a drain coupled to a first node, a source coupled to system ground, and a floating gate, wherein the nonvolatile memory cell has a programmable threshold voltage and the threshold voltage is programmed such that the nonvolatile memory cell is switched on to set the first node to system ground if the input voltage exceeds the trip-point voltage;

a first transistor including a control electrode coupled to a biasing voltage, a first terminal coupled to the first node, and a second terminal coupled to the input voltage, the control electrode for coupling the first terminal to the second terminal in response to the biasing voltage, wherein the first transistor is switched on continuously for setting the first node to the input voltage if the input voltage is less than the trip-point voltage; and

an inverter having an input coupled to the first node and an output for indicating whether the input voltage exceeds the trip-point voltage.

11. A method for indicating whether an input voltage exceeds a trip-point voltage:

applying the input voltage to a gate of a nonvolatile memory cell having a threshold voltage programmed to be the trip-point voltage, wherein the nonvolatile memory cell includes a drain coupled to a first node and a source coupled to system ground;

p1 detecting that a voltage of the first node is set to a supply voltage if the nonvolatile memory cell is switched off in response to the input voltage being less than the trip-point voltage;

indicating that the input voltage is less than the trip-point voltage if the voltage of the first node is set to the supply voltage;

detecting that a voltage of the first node is set to system ground if the nonvolatile memory cell is switched on in response to the input voltage exceeding the trip-point voltage; and

indicating that the input voltage exceeds the trip-point voltage if the voltage of the first node is set to system ground.