Switch-based microchannel planar apparatus

• US 5,495,474 A
• Filed: 09/17/1992
• Issued: 02/27/1996
• Est. Priority Date: 03/29/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Maniguet, Michael A., Saiyid, Omar A., Fisher, Michael H., Olnowich, Howard T., Lusch, Robert F.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): BLUM, RUSSELL
• Application Number:
  US07/946,204
• Time in Patent Office: 1,258 Days
• Field of Search: 370/55, 370/79, 370/85.1, 370/91, 370/60, 370/94.1, 370/53, 370/58.1, 340/826, 340/825.8
• US Class Current: 370/359
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 15/17337 Direct connection machines, e.g. completely connected computers, point to point communication networks coupling between buses G06F13/4004
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring
• CPC Class Codes: G06F 15/17393 having multistage networks, e.g. broadcasting scattering, gathering, hot spot contention, combining/decombining
• CPC Class Codes: H04J 2203/0005 Switching elements
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 12/18 for broadcast or conference , e.g. multicast
• CPC Class Codes: H04L 12/1881 with schedule organisation, e.g. priority, sequence management
• CPC Class Codes: H04L 49/256 Routing or path finding in ATM switching fabrics
• CPC Class Codes: H04L 49/3081 ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/40 Constructional details, e.g. power supply, mechanical construction or backplane
• CPC Class Codes: H04L 69/08 Protocols for interworking; Protocol conversion
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop
• CPC Class Codes: H04Q 11/0001 using optical switching
• CPC Class Codes: H04Q 11/0066 Provisions for optical burst or packet networks
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

A modularly expandable switch-based planar apparatus for insertable multiple bus-based processor cards and/or expansion cards and interconnecting the cards via a multi-stage switch network which resides on the planar apparatus. The cards require no modification or change of any kind, since the connection to the planar apparatus is made as if the planar apparatus contained the standard MicroChannel interconnection. The planar apparatus implements bus converter units to convert the standard bus interface provided by the cards to the switch network interface, so that functions provided by the cards can communicate in parallel over the switch network.

Claims

1. A switch-based, multi-node planar comprising:

a switch interconnection network means for coupling multiple nodes asynchronously through input to output port connections simultaneously;

a plurality of nodes each attached to a bus structure, and capable of configuring elements within the nodes of varying characteristics depending upon the functions implemented by various processor and/or expansion cards within the nodes;

a plurality of pluggable nodal elements capable of transmitting data to said network;

a plurality of pluggable nodal elements capable of receiving data from said network;

multiple bus converter means, each with the capability for adapting the standard bus architecture and protocol for a single multi-drop bus to said switch network architecture and protocol and each with the capability for adapting the switch network architecture and protocol to the standard bus architecture and protocol for a single multi-drop bus;

an expansion interface to said switch network comprising driver and receiver circuits and providing means of interconnecting multiple switch paths external to said planar; and

wherein said switching network operates asynchronously in relation to input signals received at each input port, needs no clock input of any kind to perform its control functions of establishing connections, and employs no buffering of data messages of any kind.

2. The apparatus of claim 1 further comprising the connection circuitry for attaching one to eight processor or expansion cards to each bus structure supported by said planar apparatus, wherein each set of said one to eight processor or expansion cards functions as a single node of the system.

3. The apparatus of claim 2, wherein said bus structure routes multi-drop data and control signals amongst said attached set of one to eight processor or expansion cards and said bus converter means internal to said planar apparatus, for the purpose of connecting the bus structure to said switch network to support parallel communication amongst other nodal elements.

4. A switch-based, multi-node planar comprising:

a switch interconnection network means for coupling multiple nodes asynchronously through input to output port connections simultaneously;

a plurality of nodes each attached to an individual multi-drop bus structure, and capable of configuring elements within the nodes of varying characteristics depending upon the functions implemented by various processor and/or expansion cards within the nodes;

a plurality of pluggable nodal elements capable of transmitting data to said network;

a plurality of pluggable nodal elements capable of receiving data from said network;

multiple multi-drop bus architecture converter means, each with the capability for adapting the standard multidrop bus architecture and protocol for a single multi-drop bus multi-drop bus to said switch network architecture and protocol and each with the capability for adapting the switch network architecture and protocol to the standard bus architecture and protocol for a single multi-drop bus; and

an expansion interface to said switch network comprising driver and receiver circuits and providing means of interconnecting multiple switch paths external to said planar; and

wherein said switching network operates asynchronously in relation to input signals received at each input port, needs no clock input of any kind to perform its control functions of establishing connections, and employs no buffering of data messages of any kind.

5. The apparatus of claim 4 further comprising the connection circuitry for attaching one to eight processor or expansion cards to each individual multi-drop bus structure supported by said planar apparatus, wherein each set of said one to eight processor or expansion cards functions as a single node of the system.

6. The apparatus of claim 4, wherein said bus structure routes multi-drop bus data and control signals amongst said attached set of one to eight processor or expansion cards and said multi-drop bus converter apparatus internal to said planar apparatus, for the purpose of connecting the multi-drop bus structure to said switch network to support parallel communication amongst other nodal elements.

7. A switch-based, multi-node planar comprising:

part of a distributed switch interconnection network means for coupling multiple local nodes asynchronously through input to output port connections simultaneously to communicate to either other local nodes located within said planar or remote nodes located external to said planar;

a plurality of nodes each attached to an individual bus structure, and capable of configuring elements within the nodes of varying characteristics depending upon the functions implemented by various processor and/or expansion cards within the nodes;

a plurality of pluggable nodal elements capable of transmitting data to said network;

a plurality of pluggable nodal elements capable of receiving data from said network;

multiple bus architecture converter means, each with the capability for adapting the bus structure protocol for a single multi-drop bus to said switch network architecture and protocol and each with the capability for adapting the switch network architecture and protocol to the bus structure protocol for a single multi-drop bus;

an expansion interface to said switch network comprising driver and receiver circuits and providing means of interconnecting multiple said planars;

wherein multiple copies of said planar can be interconnected modularly to expand the number of nodal elements supported by the apparatus; and

wherein said switching network is implemented across multiple copies of said planar, and the entire said network operates asynchronously in relation to input signals received at each input port, needs no clock input of any kind to perform its control functions of establishing connections, and employs no buffering of data messages of any kind.

8. The apparatus of claim 7 further comprising the connection circuitry for attaching one to eight processor or expansion cards to each bus structure supported by said planar apparatus, wherein each set of said one to eight processor or expansion cards functions as a single node.

9. A switch-based, multi-node planar comprising:

part of a distributed switch interconnection network means for coupling multiple local nodes asynchronously through input to output port connections simultaneously to communicate to either other local nodes located within said planar or remote nodes located external to said planar;

a plurality of nodes each attached to an individual multi-drop bus structure, and capable of configuring elements within the nodes of varying characteristics depending upon the functions implemented by various processor and/or expansion cards within the nodes;

a plurality of pluggable nodal elements capable of transmitting data to said network;

a plurality of pluggable nodal elements capable of receiving data from said network;

multiple multi-drop bus converter means, each with the capability for adapting the multi-drop bus architecture and protocol for a single multi-drop bus to said switch network architecture and protocol and each with the capability for adapting the switch network architecture and protocol to the standard bus architecture and protocol for a single multi-drop bus; and

an expansion interface to said switch network comprising driver and receiver circuits and providing means of interconnecting multiple said planars;

wherein multiple copies of said planar can be interconnected modularly to expand the number of nodal elements supported by the apparatus; and

wherein said switching network is implemented across multiple copies of said planar, and the entire said network operates asynchronously in relation to input signals received at each input port, needs no clock input of any kind to perform its control functions of establishing connections, and employs no buffering of data messages of any kind.

10. The apparatus of claim 9 further comprising the connection circuitry for attaching one to eight processor or expansion cards to each individual multi-drop bus structure supported by said planar apparatus, wherein each set of said one to eight processor or expansion cards functions as a single node of the system.

11. A switch-based, multi-node planar comprising:

a switch interconnection network means distributed amongst multiple copies of said planar and supplemented by additional switching elements implemented externally to said multiple planars for coupling multiple nodes located on the multiple planars asynchronously through input to output port connections simultaneously;

a plurality of nodes each attached to an individual standard bus structure, and capable of configuring elements within the nodes of varying characteristics depending upon the functions implemented by various processor and/or expansion cards within the nodes;

a plurality of pluggable nodal elements capable of transmitting data to said network;

a plurality of pluggable nodal elements capable of receiving data from said network;

multiple bus architecture converter means, each with the capability for adapting the standard bus architecture and protocol for a single multi-drop bus to said switch network architecture and protocol and each with the capability for adapting the switch network architecture and protocol to the standard bus architecture and protocol for a single multi-drop bus; and

an expansion interface to said switch network comprising driver and receiver circuits and providing means of interconnecting multiple said planars and additional switching elements implemented externally to said multiple planars;

wherein multiple copies of said planar can be interconnected modularly to expand the number of nodal elements supported by the apparatus by interconnecting to additional switching elements implemented externally to said multiple planars; and

wherein said switching network is implemented across multiple copies of said planar and additional switching elements implemented externally to said multiple planars, and the entire said network operates asynchronously in relation to input signals received at each input port, needs no clock input of any kind to perform its control functions of establishing connections, and employs no buffering of data messages of any kind.

12. A planar apparatus comprising:

a plurality of receptacle means each for coupling to an expansion card or processor card;

bus means for coupling each of the receptacle means to an associated one of a plurality of conversion means, each said conversion means for converting switch protocol data messages to bus protocol data messages and for converting bus protocol data messages to switch protocol data messages, each said conversion means including means for receiving a bus protocol data message over the bus means from an associated expansion card or processor card, means for sending a data message converted to switch protocol to a switch network, means for receiving a switch protocol data message from the switch network, and means for sending a data message converted to bus protocol to an associated expansion card or processor card over the bus means;

said switch network comprising;

a plurality of input ports for receiving a data message converted to switch protocol and a plurality of output ports for sending the data message converted to switch protocol;

connection means for establishing a communication path between any one of the input ports and any one of the output ports in response to a connection request received at said any one of the input ports, said communication path for transmitting a data message converted to switch protocol received at said any one of the input ports to said any one of the output ports,

said connection means including asynchronous connection means for establishing asynchronously a plurality of simultaneously active communication paths between a plurality of input ports and a plurality of output ports in response to a plurality of connection requests received separately or simultaneously at said plurality of input ports, said simultaneously active communication paths for transmitting simultaneously a plurality of data messages converted to switch protocol received separately or simultaneously at said plurality of input ports to said plurality of output ports.