Apparatus for converting pyramidal texture coordinates into corresponding physical texture memory addresses

• US 5,495,563 A
• Filed: 01/15/1991
• Issued: 02/27/1996
• Est. Priority Date: 01/15/1990
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Winser, Paul A.
• Primary Examiner(s): Nguyen, Phu K.
• Application Number:
  US07/641,228
• Time in Patent Office: 1,869 Days
• Field of Search: 395/130, 395/162, 395/164, 395/165, 395/425, 395/166, 395/400, 345/154, 345/153, 345/139
• US Class Current: 345/582
• CPC Class Codes: F16K 15/021 the valve member being a movable body around which the medium flows when the valve is open F16K15/025 - F16K15/12 take precedence
• CPC Class Codes: F16K 24/04 for venting only F16K24/02 takes precedence
• CPC Class Codes: G06T 15/04 Texture mapping
• CPC Class Codes: G06T 15/50 Lighting effects

Abstract

A display apparatus includes a host processor (14) with associated main memory (24) and a display processor with associated display memory (30) and texture memory (41'"'"'). The host processor includes an arrangement (18) for storing in the texture memory (41'"'"') at least one pyramidal or part-pyramidal array of texel values representing a given texture at at least two levels of resolution defined by respective values of a level coordinate (L) and an arrangement (18) for supplying object primitive data to the display processor (28'"'"',49). The display processor includes a processing unit (28'"'"') for generating from the object primitive data a series of pixel addresses (X,Y) for application to the display memory (30) and a corresponding series of 2-D texture coordinate pairs (U,V) each with an associated level coordinate (L), to effect a mapping of the stored texture onto the object primitive at a level or levels of resolution defined by the level coordinate (L). The texture memory includes a linearly addressed (one-dimensional) texture memory (41'"'"'). The arrangement for storing the pyramidal or part-pyramidal array of texel values includes an arrangement (D1) for storing each 2-D array thereof in linear form in the texture memory (41'"'"'). A texture management circuit (49) includes circuitry (50) for receiving and storing page location information (SWI1,W1,B1) for locating each such array in the texture memory. The texture management circuit (49) further includes circuitry (50 to 63) for using the stored page location information to convert the received texture coordinate pair (U,V) and level coordinate (L) into a linear physical texture memory address (A1).

Claims

1. A converter circuit for converting pyramidal texture coordinates into corresponding linear (one dimensional) physical texture memory addresses in an electronic display apparatus, said converter circuit comprising:

a pyramidal coordinate input for receiving a two-dimensional (2-D) texture coordinate pair and an associated level coordinate; and

means for generating, from the received coordinate pair and level coordinate, a corresponding linear (one dimensional) physical texture memory address;

wherein the means for generating the linear (one dimensional) physical texture memory address comprises;

means for generating, from the received level coordinate, page location information locating a corresponding array of texel values in a linear address space, said page location information including information defining a linear base address and a width value for the corresponding array; and

a texture address converter comprising offset generating means for combining the 2-D texture coordinate pair with the width value and the level coordinate to generate a linear offset address, and linear address generating means for combining the base address with the generated linear offset address to generate a linear physical texture memory address for application to a linearly-addressed texture memory.

2. A converter circuit as claimed in claim 1, wherein the offset generating means includes means for scaling two texture coordinates in accordance with a scaling factor defined by the level coordinate.

3. A converter circuit as claimed in claim 2, wherein the scaling factor is a power of 2 and the scaling means comprises means for bit-shifting a binary representation of each of the two texture coordinates a number of places defined by the level coordinate.

4. A converter circuit as claimed in claim 2, wherein the offset generating means comprises means for multiplying one of the two sealed texture coordinates by the width value and adding the product to the other of the two scaled texture coordinates.

5. A converter circuit as claimed in claim 4, wherein the width value is a power of two and the multiplying means comprises means for bit-shifting a binary representation of the one scaled coordinate a number of places defined by a width index received from the page location means.

6. A converter circuit as claimed in claim 3, wherein the offset generating means comprises means for multiplying one of the two scaled texture coordinates by the width value and adding the product to the other of the two scaled texture coordinates.

7. A converter circuit as claimed in claim 6, wherein the width value is a power of two and the multiplying means comprises means for bit-shifting a binary representation of the one scaled coordinate a number of places defined by a width index received from the page location means.

8. A converter circuit as claimed in claim 5, further comprising:

means for generating n further physical addresses to form a group of n+1 physical addresses all corresponding to the same level coordinate but with 2-D texture coordinate pairs offset from the received coordinate pair so as to allow parallel addressing of a patch of n+1 texel values in a stored array.

9. A converter circuit as claimed in claim 1, further comprising:

means for generating n further physical addresses to form a group of n+1 physical addresses all corresponding to the same level coordinate but with 2-D texture coordinate pairs offset from the received coordinate pair so as to allow parallel addressing of a patch of n+1 texel values in a stored array.

10. A converter circuit as claimed in claim 9, wherein said converter circuit further comprising:

means for generating a further physical address corresponding to the same 2-D texture coordinate pair but with a level coordinate offset from the received coordinate; and

selection means responsive to the page location information whereby the physical address and the further physical address may be applied to different ones of two separate, parallel-addressable texture memory banks.

11. A converter circuit as claimed in claim 1, said circuit arrangement further comprising:

means for generating a further physical address corresponding to the same 2-D texture coordinate pair but with a level coordinate offset from the received level coordinate; and

selection means responsive to the page location information whereby the physical addresses) and the further physical address may be applied to different ones of two separate, parallel-addressable texture memory banks.

18. A converter circuit as claimed in claim 1, in which the means for generating page location information comprises:

a page table memory for storing page location information;

means for entering texture memory locations into the page table memory as the page location information, said texture memory locations defining the locations within the texture memory where texel value arrays corresponding to a given page are stored; and

means for reading page locations from the page table memory in response to received texture coordinates and level coordinates.

12. A display apparatus comprising a host processor with associated main memory for the storage of object primitive data and texture definitions and a display processor with associated display memory and texture memory, the host processor comprising:

means for storing in the texture memory at least one pyramidal array of texel values, said pyramidal array comprising a plurality of two-dimensional (2-D) arrays of texel values representing a given 2-D modulation pattern at at least two levels of resolution defined by respective values of a level coordinate; and

means for supplying object primitive data to the display processor, including an indication that a pattern of modulation is to be applied to the object primitive in accordance with texel values stored in the pyramidal array in the texture memory;

the display processor comprising;

means for generating from the object primitive data a series of pixel addresses for application to the display memory and a corresponding series of 2-D texture coordinate pairs each with an associated level coordinate, to effect a mapping of the stored texel values representing a pattern or modulation on to the object primitive at a level or levels of resolution defined by the associated level coordinate; and

means for receiving each 2-D texture coordinate pair and associated level coordinate and for generating therefrom a physical texture memory address for application to the texture memory;

wherein the texture memory comprises a linearly addressed (one-dimensional) texture memory, the means for storing the pyramidal array of texel values comprises means for storing each 2-D array in linear form in the texture memory and means for generating page location information for locating each such array in the texture memory, and the means for generating the physical texture memory address comprises;

a converter circuit for converting pyramidal texture coordinates into corresponding linear (one-dimensional) physical texture memory addresses in an electronic display apparatus, said converter circuit comprising;

a pyramidal coordinate input for receiving a two-dimensional (2-D) texture coordinate pair and an associated level coordinate; and

means for generating, from the received coordinate pair and level coordinate, a corresponding linear (one-dimensional) physical texture memory address;

wherein the means for generating the linear/one-dimensional) physical texture memory address comprises;

means for generating, from the received level coordinate, page location information locating a corresponding array of texel values in a linear address space, said page location information including information defining a linear base address and a width value for the corresponding array; and

a texture address converter comprising offset generating means for combining the 2-D texture coordinate pair with the width value and the level coordinate to generate a linear offset address, linear address generating means for combining the base address with the generated linear offset address to generate a linear physical texture memory address for application to a linearly-addressed texture memory, and means for generating n further physical addresses to form a group of n+I physical addresses all corresponding to the same level coordinate but with 2-D texture coordinate pairs offset from the received coordinate pair so as to allow parallel addressing of a patch of n+1 texel values in a stored array.

13. A display apparatus as claimed in claim 12, wherein the linear texture memory is divided into n+1 parallel-addressed memories and the texel value storage means are arranged to distribute the texel values being stored among the n+1 memories in an interleaved manner, the display apparatus further comprising 2-D interpolation means responsive to fractional parts of the 2-D texture coordinate pair for combining texel values of a 2-D patch into a single interpolated value.

14. A display apparatus as claimed in claim 13, further comprising means for generating a 2-D array of texel values for storage in the texture memory as part of a pyramidal array by causing systematic readout and 2-D interpolation of the texel values in a previously stored 2-D array forming a first level of the pyramidal array, and feedback means for storing the resulting interpolated texel values in the memory to form a 2-D array of texel values to form a second, lower-resolution level of the pyramidal array.

15. A display apparatus as claimed in claim 13, wherein the texture memory comprises separate first and second linearly addressable texture memory banks, the texel value storage means being arranged to store the 2-D arrays forming successive levels of a given pyramidal or part-pyramidal array alternately in the first and second texture memory banks, the display apparatus further comprising an interpolator responsive to a fractional part of the level coordinate for combining texel values from both levels into a single interpolated texel value.

16. A display apparatus as claimed in claim 14, wherein the texture memory comprises separate first and second linearly addressable texture memory banks, the texel value storage means being arranged to store the 2-D arrays forming successive levels of a given pyramidal or part pyramidal array alternately in the first and second texture memory banks, the display apparatus further comprising an interpolator responsive to a fractional part of the level coordinate for combining texel values from both levels into a single interpolated texel value.

17. A display apparatus as claimed in claim 12, wherein the texture memory comprises separate first and second linearly addressable texture memory banks, the texel value storage means being arranged to store the 2-D arrays forming successive levels of a given pyramidal or part-pyramidal array alternately in the first and second texture memory banks, the display apparatus further comprising an interpolator responsive to a fractional part of the level coordinate for combining texel values from both levels into a single interpolated texel value.