On demand powering of necesssary portions of execution unit by decoding instruction word field indications which unit is required for execution

• US 5,495,617 A
• Filed: 06/02/1995
• Issued: 02/27/1996
• Est. Priority Date: 08/10/1984
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Yamada, Kouichi
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Ellis, Richard L.
• Application Number:
  US08/460,745
• Time in Patent Office: 270 Days
• Field of Search: 395/375, 395/750, 395/800
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 9/226 Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A microprocessor of CMOS structure includes at least an execution unit and a control unit including an instruction register adapted to receive and store instructions to be executed by the microprocessor and an instruction decoder receiving the instruction from the instruction register and outputting a control signal. Furthermore, the processor comprises a second instruction decoder receiving at least a portion of the instruction applied from the instruction register to the first instruction decoder so as to supply a standby control signal to the execution unit.

Claims

1. A microprocessor of CMOS structure comprising:

(a) an execution unit,

(b) a control unit including;

a bus,

an instruction register coupled to said bus to receive and store instructions to be executed by the microprocessor,

a first instruction decoder coupled to said instruction register for receiving an instruction from the instruction register and for outputting at least one control signal to the execution unit,

a second instruction decoder connected to said instruction register to receive at least a portion of said instruction for generating a standby cancel signal to the execution unit for placing said execution unit in an operational mode,

(c) said execution unit responsive to said at least one control signal and including;

a microinstruction bus, and

a microprogram ROM read controller coupled to receive said standby cancel signal from the second instruction decoder and also coupled to said microinstruction bus to detect an END microinstruction for generating a halt signal in response thereto, said halt signal being supplied to said execution unit,

(d) wherein said execution unit is placed into a standby mode in response to said halt signal, said execution unit normally being placed in said standby condition so that average power consumption is reduced, and

wherein said execution unit further includes a carry lookahead circuit having a common bias line and a carry lookahead biasing circuit connected to receive said halt signal and coupled to said common bias line of the carry lookahead circuit for supplying a bias current thereto when said halt signal is inactive and to stop the supply of the bias current when said halt signal is active.

2. A coprocessor system of CMOS structure comprising:

(a) an execution unit,

(b) a control unit including;

a bus,

an instruction register coupled to said bus to receive and store instructions to be executed, each of which includes an instruction part and information designating a processor which is required to execute said instruction part, said processor designating information being composed of a plurality of most significant bits of said instruction,

a first instruction decoder coupled to the instruction register to receive an instruction from the instruction register and to output at least one control signal to the execution unit,

a second instruction decoder coupled to said bus for receiving the most significant bits of said instruction for generating a standby cancel signal to said execution unit when said processor designating information designates said coprocessor so that said execution unit is brought into an operating condition in response to said standby cancel signal and executes a predetermined processing in accordance with said one control signal,

a microprogram ROM read controller coupled to a microinstruction bus to detect an END microinstruction by detecting a predetermined number of most significant bits of microinstructions and to generate a halt signal in response to said predetermined number of most significant bits of microinstructions and wherein the execution unit is put into a standby mode in response to the halt signal; and

a carry lookahead circuit in said execution unit and a carry lookahead biasing circuit which is coupled to a common bias line of the carry lookahead circuit for supplying a bias current to the common bias line of the carry lookahead circuit in response to a standby control signal and to stop the supply of the bias current in response to the halt signal.

3. A microprocessor of CMOS structure comprising:

an execution unit;

a control unit including;

an instruction register receiving and storing instructions to be executed by the microprocessor;

a first instruction decoder receiving an instruction from the instruction register and outputting at least one control signal,

a second instruction decoder receiving at least a portion of the instruction applied from the instruction register to the first instruction decoder and supplying a standby control signal to the execution unit,

wherein each instruction stored in the instruction register includes a field designating a type of instruction, and wherein the second instruction decoder decodes the field of the instruction and operates to supply the standby control signal to the execution unit to put at least one portion of the execution unit into a standby mode when the field indicates that the given instruction is of a first type, said standby mode being a non-operating condition of said execution unit for reducing an average power consumption of said microprocessor to a level at least one order of magnitude less than an average power consumption of an operating condition of said execution unit, and to inhibit the standby control signal to put the at least one portion of the execution unit into the operating condition when the field indicates that the instruction is of a second type.

4. A microprocessor as claimed in claim 3, wherein the portion of the execution unit put into the standby mode is a microprogram ROM read-out circuit.

5. A microprocessor as claimed in claim 3, wherein the portion of the execution unit put into the standby mode is a carry look-ahead circuit in an arithmetic logic circuit of the execution unit.

6. A microprocessor as claimed in claim 3, wherein the microprocessor is a coprocessor.

7. A microprocessor as claimed in claim 6, wherein the second instruction decoder receives a number of most significant bits of the instruction loaded to the first instruction decoder.

8. A microprocessor as claimed in claim 7, wherein the instruction loaded to the first instruction decoder includes a first portion of most significant bits which indicates whether a given instruction is directed to the coprocessor and a next portion of most significant bits which designates whether the given instruction needs to read a microprogram, and wherein the second instruction decoder includes a first logic circuit receiving the first portion of most significant bits for generating a signal indicating whether said instruction is directed to said coprocessor, a second logic circuit receiving the the next portion of most significant bits for generating a signal for indicating whether said instructions requires a microprogram read and an AND circuit receiving the outputs of the first and second logic circuits for generating a standby cancel signal.

9. A microprocessor as claimed in claim 8 further including a microprogram ROM read controller detection an AND microinstruction by detecting the first portion of most significant bits of microinstructions and generating a halt signal and wherein the execution unit is put into the standby mode in response to the halt signal.

10. A microprocessor as claimed in claim 9 further including a microprogram ROM read-out circuit which is associated to a microprogram ROM, said readout circuit being rendered operational in response to the standby cancel signal and not operational in response to the halt signal.

11. A microprocessor of CMOS structure comprising:

an execution unit;

a control unit including;

an instruction register receiving and storing instructions to be executed by the microprocessor;

a first instruction decoder receiving an instruction from the instruction register and outputting at least one control signal, and

a second instruction decoder receiving at least a portion of the instruction applied from the instruction register to the first instruction decoder and supplying a standby control signal to the execution unit, wherein

each instruction stored in the instruction register includes a field designating a type of instruction, and wherein the second instruction decoder decodes the field of the instruction and operates to supply the standby control signal to the execution unit to put at least one portion of the execution unit into a standby mode when the field indicates that the given instruction is of a first type, and to inhibit the standby control signal to put the at least one portion of the execution unit into an operating condition when the field indicates that the instruction is of a second type;

the microprocessor is a coprocessor;

the second instruction decoder receives a number of most significant bits of the instruction loaded to the first instruction decoder; and

the instruction loaded to the first instruction decoder includes a first portion of most significant bits which indicates whether a given instruction is directed to the coprocessor and a next portion of most significant bits which designates whether the given instruction needs to read a microprogram and wherein the second instruction decoder includes a first logic circuit receiving the first portion of most significant bits for generating a signal indicating whether said instruction is directed to said coprocessor a second logic circuit receiving the next portion of most significant bits for generating a signal for indicating whether said instructions requires a microprogram read and an AND circuit receiving the outputs of the first and second logic circuits for generating a standby cancel signal; and

said microprocessor further includes a microprogram ROM read controller detecting an AND microinstruction by detecting the first portion of most significant bits of microinstructions and generating a halt signal and wherein the execution unit is put into the standby mode in response to the halt signal; and

a carry look-ahead circuit in the execution unit and a carry lookahead biasing circuit which is associated with the carry lookahead circuit and adapted to supply a bias voltage to the carry look-ahead circuit in response to the standby cancel signal and to make it non-operational in response to the halt signal.