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On demand powering of necesssary portions of execution unit by decoding instruction word field indications which unit is required for execution

  • US 5,495,617 A
  • Filed: 06/02/1995
  • Issued: 02/27/1996
  • Est. Priority Date: 08/10/1984
  • Status: Expired due to Fees
First Claim
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1. A microprocessor of CMOS structure comprising:

  • (a) an execution unit,(b) a control unit including;

    a bus,an instruction register coupled to said bus to receive and store instructions to be executed by the microprocessor,a first instruction decoder coupled to said instruction register for receiving an instruction from the instruction register and for outputting at least one control signal to the execution unit,a second instruction decoder connected to said instruction register to receive at least a portion of said instruction for generating a standby cancel signal to the execution unit for placing said execution unit in an operational mode,(c) said execution unit responsive to said at least one control signal and including;

    a microinstruction bus, anda microprogram ROM read controller coupled to receive said standby cancel signal from the second instruction decoder and also coupled to said microinstruction bus to detect an END microinstruction for generating a halt signal in response thereto, said halt signal being supplied to said execution unit,(d) wherein said execution unit is placed into a standby mode in response to said halt signal, said execution unit normally being placed in said standby condition so that average power consumption is reduced, andwherein said execution unit further includes a carry lookahead circuit having a common bias line and a carry lookahead biasing circuit connected to receive said halt signal and coupled to said common bias line of the carry lookahead circuit for supplying a bias current thereto when said halt signal is inactive and to stop the supply of the bias current when said halt signal is active.

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