Method for forming a nonvolatile memory device

• US 5,496,756 A
• Filed: 01/30/1995
• Issued: 03/05/1996
• Est. Priority Date: 04/29/1994
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Kirsch, Howard C., Sharma, Umesh, Hayden, Jim
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US08/340,914
• Time in Patent Office: 400 Days
• Field of Search: 437/21, 437/43, 437/52, 437/83, 437/915, 257/640, 257/641, 257/760, 257/324
• US Class Current: 438/258
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

Abstract

A nonvolatile SRAM cell (20) includes a six-transistor SRAM cell portion (22) and a three-transistor nonvolatile memory portion (30). The nonvolatile memory portion (30) is connected to one storage node (101) of the SRAM cell portion (22). The nonvolatile SRAM cell (20) is three-dimensionally integrated in four layers of polysilicon. The nonvolatile memory portion (30) includes a thin film memory cell (32) having an oxide-nitride-oxide structure (41), and is programmable with a relatively low programming voltage. The three-dimensional integration of the nonvolatile SRAM cell (20) and relatively low programming voltage results in lower power consumption and smaller cell size.

Claims

1. A method for forming an undergated thin film nonvolatile memory device comprising the steps of:

providing an insulating substrate;

forming a gate electrode overlying the insulating substrate;

forming a sidewall spacer laterally adjacent to an edge of the gate electrode;

depositing a first oxide layer overlying the insulating substrate and over a top surface of the gate electrode;

depositing a silicon nitride layer over the first oxide layer;

oxidizing a surface of the silicon nitride layer to form a relatively thin second oxide layer overlying the silicon nitride layer, wherein the second oxide layer is relatively thin compared to the first oxide layer;

depositing a semiconductive layer overlying the second oxide layer; and

implanting source and drain regions in the semiconductive layer.

2. The method of claim 1, wherein the step of oxidizing a surface of the silicon nitride layer comprises oxidizing the silicon nitride layer to form the second oxide layer having a thickness of 15 to 20 angstroms.

3. The method of claim 1, wherein the step of implanting source and drain regions in the semiconductive layer comprises asymmetrically aligning the source and drain regions with the gate electrode.

4. The method of claim 1, wherein the semiconductive layer is chemically deposited polysilicon.

5. The method of claim 1, further comprising the steps of:

forming a dielectric layer overlying the semiconductive layer;

forming openings in the dielectric layer to expose a contact portion of each of the source and drain regions; and

forming an electrical contact to the contact portions of each of the source and drain regions.

6. A method for forming a thin film nonvolatile memory device comprising the steps of:

providing an insulating substrate;

depositing a semiconductive layer overlying the insulating substrate;

depositing a gate oxide layer overlying the semiconductive layer;

forming first and second gate electrodes overlying the gate oxide layer;

etching a window region in the gate oxide layer between the first and second gate electrodes;

forming a first oxide layer overlying the first and second gate electrodes and the window region;

depositing a silicon nitride layer overlying the first oxide layer;

depositing a second oxide layer overlying the silicon nitride layer, wherein the second oxide layer is relatively thick compared to the first oxide layer;

forming a third gate electrode overlying the second oxide layer between the first and second gate electrodes, the third gate electrode overlying a portion of the first gate electrode and the second gate electrode; and

implanting source and drain regions in the semiconductive layer.

7. The method of claim 6, wherein the step of forming the first oxide layer comprises forming the first oxide layer having a thickness of 15 to 20 angstroms.

8. The method of claim 6, wherein the semiconductive layer is chemically deposited polysilicon.

9. The method of claim 6, further comprising the steps of:

forming a dielectric layer overlying the gate oxide layer, the second oxide layer and the third gate electrode;

forming openings in the dielectric layer to expose a contact portion of each of the source and drain regions; and

forming an electrical contact to the contact portions of each of the source and drain regions.