Dynamic random access memory array having a cross-point layout, tungsten digit lines buried in the substrate, and vertical access transistors
First Claim
1. A dynamic random access memory array fabricated on a semiconductor substrate comprising:
- (a) a series of parallel metal digit lines, each digit line being at least partially buried within a dielectrically lined trench in the substrate; and
(b) a plurality of individual memory cells arranged in a cross-point layout, each cell having both a cell capacitor located at a level that is above the digit lines and an insulated-gate field-effect access transistor, said transistor having first and second source/drain regions and a vertical channel, said source/drain regions and said channel being formed in expitaxially-grown semiconductor material, said transistor selectively coupling the capacitor to one of said digit lines.
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Abstract
This invention is a DRAM array having stacked-capacitor cells of potentially 4F2 surface area (F being the photolithographic minimum feature width), and a 5-mask process for fabricating such an array. The array has a cross-point cell layout (i.e., a memory cell is located at each intersection of each digit line and each word line) and tungsten digit lines formed using a damascene process buried in the substrate. Each cell in the array has a vertical transistor, with the source/drain regions and channel region of the transistor being formed from epitaxially grown single crystal silicon. The stacked capacitor is fabricated on top of the vertical transistor.
295 Citations
19 Claims
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1. A dynamic random access memory array fabricated on a semiconductor substrate comprising:
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(a) a series of parallel metal digit lines, each digit line being at least partially buried within a dielectrically lined trench in the substrate; and (b) a plurality of individual memory cells arranged in a cross-point layout, each cell having both a cell capacitor located at a level that is above the digit lines and an insulated-gate field-effect access transistor, said transistor having first and second source/drain regions and a vertical channel, said source/drain regions and said channel being formed in expitaxially-grown semiconductor material, said transistor selectively coupling the capacitor to one of said digit lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 10)
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- 8. An array of dynamic random access memory cells fabricated on a single-crystal semiconductor substrate, each cell comprising a vertical access transistor, each transistor having a channel region and first and second source/drain regions, said channel region and said source/drains regions being formed from selectively-grown, epitaxial silicon that is part of the substrate crystal which further comprises a series of parallel metal digit lines, each digit line being at least partially buried within a dielectrically lined trench in the substrate.
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16. A dynamic random access memory array fabricated on a single-crystal semiconductor substrate comprising:
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(a) a series of parallel metal digit lines, each digit line being at least partially buried within a dielectrically lined trench in the substrate; and (b) a plurality of individual memory cells arranged in a cross-point layout, each cell having both a cell capacitor located at a level that is above the digit lines and an insulated-gate field-effect access transistor, said transistor having a first source/drain region coupled to said capacitor, a second source/drain region coupled to one of said digit lines, and a vertical channel, said source/drain regions and said channel being formed in expitaxially-grown semiconductor material that is part of the single crystal which constitutes the substrate, said transistor selectively coupling the capacitor to one of said digit lines. - View Dependent Claims (17, 18, 19)
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Specification