Semiconductor memory device having separately biased wells for isolation

• US 5,497,023 A
• Filed: 12/08/1994
• Issued: 03/05/1996
• Est. Priority Date: 09/25/1985
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Hori, Ryoichi, Shimohigashi, Katsuhiro, Saito, Yoshikasu, Kobayashi, Yutaka, Uchida, Hideaki, Kitsukawa, Goro, Watanabe, Takao, Itoh, Kiyoo, Nakazato, Shinji, Yamamura, Masahiro, Ikeda, Takahide, Homma, Noriyuki, Tanba, Nobuo
• Primary Examiner(s): Limanek, Robert P.
• Application Number:
  US08/352,238
• Time in Patent Office: 453 Days
• Field of Search: 257/548, 257/394, 257/901
• US Class Current: 257/394
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H01L 27/0218 of field effect structures
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: Y10S 257/901 MOSFET substrate bias
• CPC Class Codes: Y10S 257/904 with passive components,, e.g. polysilicon resistors

Abstract

Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

Claims

1. A semiconductor integrated circuit device comprising:

a semiconductor substrate having a main surface of a first conductivity type;

a first semiconductor region of a second conductivity type, opposite to said first conductivity type, formed in said main surface of said semiconductor substrate;

a second semiconductor region of said first conductivity type formed in said first semiconductor region;

a first MISFET of said second conductivity type formed in a first region of said main surface of said semiconductor substrate, said first region being different from said first semiconductor region; and

a second MISFET of said second conductivity type formed in a surface of said second semiconductor region,

wherein a first voltage is to be applied to said first semiconductor region, a second voltage is to be applied to said second semiconductor region, and a third voltage is to be applied to said main surface of said semiconductor substrate, such that said first voltage is to be applied to said first semiconductor region for electrically isolating said second semiconductor region from said main surface of said semiconductor substrate, and wherein a value of said second voltage is to be different from that of said third voltage.

2. A semiconductor integrated circuit device according to claim 1, further comprising a third MISFET of said first conductivity type formed in a second region of a surface of said first semiconductor region,

wherein said second region is different from said second semiconductor region.

3. A semiconductor integrated circuit device according to claim 1, further comprising voltage devices for applying said first voltage, said second voltage and said third voltage.

4. A semiconductor integrated circuit device according to claim 3, wherein said first conductivity type is p-type and said second conductivity type is n-type, and wherein a value of said first voltage is greater than that of said second voltage and that of said third voltage.

5. A semiconductor integrated circuit device according to claim 3, further comprising a memory cell formed in said surface of said second semiconductor region and a peripheral circuit formed in said first region of said main surface of said semiconductor substrate, wherein said memory cell includes said second MISFET and said peripheral circuit includes said first MISFET.

6. A semiconductor integrated circuit device according to claim 5, wherein said first conductivity type is p-type and said second conductivity type is n-type, and wherein a value of said first voltage is greater than that of said second voltage and that of said third voltage.

7. A semiconductor integrated circuit device according to claim 3, wherein said value of said second voltage is lower than that of said third voltage.

8. A semiconductor integrated circuit device according to claim 7, further comprising a bias generator coupled between a first power supply voltage and a second power supply voltage and for providing a bias voltage, formed in said main surface of said semiconductor substrate, wherein said second power supply voltage is lower than that of said first power supply voltage, and said bias voltage is lower than that of said second power supply voltage, and wherein said second voltage applied to said second semiconductor region corresponds to said bias voltage provided by said bias generator.

9. A semiconductor integrated circuit device comprising:

a semiconductor substrate having a main surface of a first conductivity type;

a first semiconductor region of a second conductivity type, opposite to said first conductivity type, formed in said main surface of said semiconductor substrate;

a second semiconductor region of said first conductivity type formed in said first semiconductor region;

a first MISFET of said second conductivity type formed in a first region of said main surface of said semiconductor substrate, said first region being different from said first semiconductor region;

a second MISFET of said second conductivity type formed in a surface of said second semiconductor region;

a first voltage device to apply a first voltage to said first semiconductor region;

a second voltage device to apply a second voltage to said second semiconductor region; and

a third voltage device to apply a third voltage to said main surface of said semiconductor substrate,

such that said first voltage is applied to said first semiconductor region for electrically isolating said second semiconductor region from said main surface of said semiconductor substrate, and wherein a value of said second voltage is different from that of said third voltage.

10. A semiconductor integrated circuit device comprising:

a semiconductor substrate having a main surface of a first conductivity type;

a first semiconductor region of a second conductivity type, opposite to said first conductivity type, formed in said main surface of said semiconductor substrate so as to form a first PN junction between said first semiconductor region and said main surface of said semiconductor substrate;

a second semiconductor region of said first conductivity type formed in said first semiconductor region so as to form a second PN junction between said second semiconductor region and said first semiconductor region;

a first MISFET of said second conductivity type formed in a first region of said main surface of said semiconductor substrate, said first region being different from said first semiconductor region; and

a second MISFET of said second conductivity type formed in a surface of said second semiconductor region,

wherein a first voltage is to be applied to said first semiconductor region, a second voltage is to be applied to said second semiconductor region, and a third voltage is to be applied to said main surface of said semiconductor substrate, so that said second PN junction is reverse biased by said first and second voltages, and said first PN junction is reverse biased by said first and second voltages, and wherein a value of said second voltage is to be different from that of said third voltage.

11. A semiconductor integrated circuit device according to claim 10, further comprising voltage devices for applying said first voltage, said second voltage and said third voltage.

12. A method of operating a semiconductor integrated circuit device, the semiconductor integrated circuit device comprising a semiconductor substrate having a main surface of a first conductivity type;

a first semiconductor region of a second conductivity type, opposite to said first conductivity type, formed in said main surface of said semiconductor substrate;

a second semiconductor region of said first conductivity type, formed in said first semiconductor region;

a first MISFET of said second conductivity type formed in a first region of said main surface of said semiconductor substrate, said first region being different from said first semiconductor region; and

a second MISFET of said second conductivity type formed in a surface of said second semiconductor region, said method comprising the steps of;

applying a first voltage to said first semiconductor region;

applying a second voltage to said second semiconductor region; and

applying a third voltage to said main surface of said semiconductor substrate,

wherein said first voltage electrically isolates said second semiconductor region from said main surface of said semiconductor substrate, and wherein a value of said second voltage is different from that of said third voltage.

13. A method according to claim 12, wherein said first conductivity type is p-type and said second conductivity type is n-type, and wherein a value of said first voltage is greater than that of said second voltage and that of said third voltage.

14. A method according to claim 12, wherein said value of said second voltage is lower than that of said third voltage.

15. A method of operating a semiconductor integrated circuit device, the semiconductor integrated circuit device comprising a semiconductor substrate having a main surface of a first conductivity type;

a first semiconductor region of a second conductivity type, opposite to said first conductivity type, formed in said main surface of said semiconductor substrate so as to form a first PN junction between said first semiconductor region and said main surface of said semiconductor substrate;

a second semiconductor region of said first conductivity type formed in said first semiconductor region so as to form a second PN junction between said second semiconductor region and said first semiconductor region;

a first MISFET of said second conductivity type formed in a first region of said main surface of said semiconductor substrate, said first region being different from said first semiconductor region; and

a second MISFET of said second conductivity type formed in a surface of said second semiconductor region, said method comprising the steps of;

applying a first voltage to said first semiconductor region;

applying a second voltage to said second semiconductor region; and

applying a third voltage to said main surface of said semiconductor substrate,

wherein said second PN junction is reverse biased by said first and second voltages, and said first PN junction is reverse biased by said first and second voltages, and wherein a value of said second voltage is different from that of said third voltage.